Abstract: A filter and an operating method thereof are provided. The filter includes a logic circuit, a power circuit and a filter circuit. The logic circuit provides a switching control signal. The power circuit is coupled to the logic circuit. The filter circuit is coupled to the power circuit and the logic circuit. The filter circuit includes an amplifier, a first capacitor and a first transistor. An output end of the amplifier is coupled to the logic circuit, and provides an output signal. The first capacitor is coupled between an input end and output end of the amplifier. The first transistor is connected in parallel with the first capacitor. A control end of the first transistor is coupled to the power circuit. The logic circuit provides a switching control signal to the power circuit according to the output signal. The power circuit supplies a control voltage to the first transistor according to the switching control signal.

Abstract: A DC-DC converting controller is disclosed. The DC-DC controller includes a current sensing unit, a parameter setting pin, a parameter setting unit and an error amplifier. The current sensing unit provides a sensing current. The parameter setting pin is coupled to an external parameter setting unit. The parameter setting unit is coupled to the current sensing unit and the parameter setting pin. The parameter setting unit has an internal parameter setting unit. The parameter setting unit generates a droop current according to the external parameter setting unit and the sensing current. The error amplifier includes a first input terminal and a second input terminal. The first input terminal receives an output feedback voltage and the second input terminal receives a first reference voltage. The second input terminal is coupled to a terminal of the internal parameter setting unit.

Abstract: A pulse-width modulation (PWM) controller including an output pin, a temporary voltage generation circuit and a tri-state voltage generation circuit is disclosed. The temporary voltage generation circuit includes a voltage-dividing unit and a control unit. The voltage-dividing unit is coupled to the output pin and the control unit respectively. The control unit receives an enable signal and a PWM signal. The tri-state voltage generation circuit is coupled to the temporary voltage generation circuit and the output pin and receives the enable signal, the PWM signal and a tri-state input voltage. When the PWM controller is operated in a tri-state mode, the control unit controls the voltage-dividing unit to provide a temporary voltage to the output pin according to the enable signal and PWM signal, and then the tri-state voltage generation circuit provides a tri-state voltage to the output pin according to the enable signal and PWM signal.

Abstract: A transient voltage suppression device including a substrate and a first transient voltage suppressor is provided. The substrate includes a device region and a seal-ring region. The seal-ring region surrounds the device region. A first transient voltage suppressor is located in the device region. The first transient voltage suppressor includes a first well region having a first conductivity type, a first doped region having a second conductivity type, and a second doped region having the second conductivity type. The first well region is located in the substrate of the device region. The first doped region is located in the first well region. The second doped region is located in the first well region. A third doped region having the second conductivity type is located in the substrate of the seal-ring region, and the third doped region is electrically connected to the first doped region.

Abstract: A transient voltage suppressor includes a substrate, a first well, a second well, a third well, a first electrode, a second electrode and a doped region. The first well is formed in the substrate and near a surface of the substrate. The second well is formed in the first well and near the surface. The third well is formed in the first well and near the surface. There is a gap between the second well and the third well. The first electrode and second electrode are formed in the second well and near the surface respectively. The first well and first electrode have a first electrical property. The second well, third well and second electrode have a second electrical property. The doped region is formed between the first electrode and second electrode and near the surface and electrically connected with the first well and third well.

Abstract: A DC-DC converting controller, coupled to an output stage including a phase node and an operation switch coupled between the phase node and a ground voltage, includes a pulse-width modulation (PWM) unit, a zero-level comparator and a threshold voltage generation unit. The PWM unit, coupled to the output stage, provides the PWM signal to the output stage for controlling the operation switch. The zero-level comparator has a first input terminal, a second input terminal and an output terminal. The first input terminal is coupled to the phase node. The output terminal, coupled to the PWM unit, provides a zero-current voltage to adjust the PWM signal. The threshold voltage generation unit, coupled to the phase node and zero-level comparator, provides the threshold voltage to the second input terminal. The threshold voltage generation unit dynamically adjusts threshold voltage according to a default voltage and the phase voltage on the phase node.

Abstract: A dc-dc converting circuit and a method for controlling the same are provided. The dc-dc converting circuit includes an output stage, a mode detection circuit, a PWM signal generating circuit and a ramp signal generating circuit. The output stage provides an output voltage. The mode detection circuit provides a mode detection signal. The PWM generating circuit provides a time signal to the output stage. When the dc-dc converting circuit enters a continuous conduction mode from a discontinuous conduction mode, the ramp signal generating circuit provides a second ramp signal to the PWM signal generating circuit in a preset time according to the mode detection signal. The ramp signal generating circuit provides a first ramp signal to the PWM signal generating circuit after the preset time. A slope of the second ramp signal is greater than a slope of the first ramp signal.

Abstract: A transient voltage suppressor includes a substrate, a first well, a second well, a first electrode, a second electrode, a doped region and a heavily-doped region. The first well is formed in the substrate and near a surface of substrate. The second well is formed in the first well and near the surface. The first electrode and second electrode are formed in the second well and near the surface respectively. The first well and first electrode have a first electrical property. The second well and second electrode have a second electrical property. The doped region is formed between the first electrode and second electrode and near the surface and electrically connected with the first well and second well. The heavily-doped region is formed under the doped region. The heavily-doped region has the same electrical property with the doped region and has higher doping concentration than the doped region.

Abstract: A current mirror calibration circuit, coupled to an error amplifier of a pulse-width modulation controller, includes a first voltage generation unit, a second voltage generation unit, a calibration unit and a current mirror circuit. During an initial period, the first voltage generation unit and second voltage generation unit provide a first default voltage and a second default voltage respectively. The current mirror circuit includes a first current unit and a second current unit. The first current unit receives an original current. The second current unit generates a mirror current having a proportional relationship with original current. The first current unit has a first node coupled to the first voltage generation unit and a second node coupled to a third default voltage. The second current unit has a third node coupled to the second voltage generation unit and calibration unit and a fourth node coupled to calibration unit and an output terminal of error amplifier.

Abstract: Provided is a power transistor device including a substrate, a first electrode, and a second electrode. The substrate has an active region and a terminal region. The terminal region surrounds the active region. The substrate includes a first trench and a second trench. The first trench is disposed within the active region and adjacent to the terminal region. The second trench is disposed within the terminal region and adjacent to the active region. The first electrode and the second electrode are respectively disposed in the first trench and the second trench. The first electrode and the second electrode both are electrically floating.

Abstract: A power semiconductor device including a substrate having an active region and a terminal region is provided. The terminal region surrounds the active region. A first epitaxial layer is disposed on the substrate in the active region and the terminal region. A second epitaxial layer is disposed on the first epitaxial layer. The second epitaxial layer includes a first termination trench, a second termination trench, and a third termination trench. The first termination trench is disposed in the terminal region and is adjacent to the active region. The second termination trench is disposed in the terminal region. The third termination trench is disposed in the terminal region. The second termination trench is located between the first termination trench and the third termination trench. The third termination trench has a third electrode electrically connected to a drain.

Abstract: A DC-DC converting controller coupled to an output stage and an external resistor network and providing a pulse-width-modulation (PWM) signal to control the output stage to provide an output voltage is disclosed. The DC-DC converting controller includes a sensing circuit, a droop current circuit, a first pin and a PWM signal control loop. The sensing circuit, coupled to the output stage, provides a sensing current. The droop current circuit, coupled to the sensing circuit, provides a droop current according to the sensing current. The first pin, coupled to the droop current circuit and external resistor network, provides the droop current to make the external resistor network provide a second reference voltage. The PWM signal control loop, coupled to the external resistor network, generates a PWM signal according to the output voltage and the second reference voltage. The droop current is reduced to a default value with a default time.

Abstract: Provided is an electrostatic discharge protection device including a first work area and a second work area. The first work area is configured to form a face-to-face connected diode string. The first work area includes a plurality of first sub-work areas. Each of the first sub-work areas includes a first doped region of a first conductivity type disposed in a substrate, a second doped region of a second conductivity type disposed in the substrate and surrounding the first doped region, and a third doped region of the second conductivity type disposed below the second doped region. The second work area is configured to form at least one diode. The second work area includes at least one second sub-work area. The second sub-work area includes a fourth doped region of the second conductivity type disposed in the substrate. Besides, the fourth doped region is electrically connected to the first doped region.

Abstract: A transient voltage suppression device including a substrate and a first transient voltage suppressor is provided. The substrate includes a device region and a seal-ring region. The seal-ring region surrounds the device region. A first transient voltage suppressor is located in the device region. The first transient voltage suppressor includes a first well region having a first conductivity type, a first doped region having a second conductivity type, and a second doped region having the second conductivity type. The first well region is located in the substrate of the device region. The first doped region is located in the first well region. The second doped region is located in the first well region. A third doped region having the second conductivity type is located in the substrate of the seal-ring region, and the third doped region is electrically connected to the first doped region.

Abstract: The present invention provides a semiconductor device that can achieve miniaturization or thinning of the size of the package while maintaining the characteristic of the MOSFET and reducing the on-resistance value, and a portable apparatus using the same. The gate electrodes 26 and 28 of the semiconductor chip 10 are disposed in the vicinity of the two side surfaces of the longitudinal direction (the x axis direction on the page) of the package 2, and the gate terminal 13 and 14 that is mounted with the gate electrodes 26 and 28 in a flip-chip manner are extended in the longitudinal direction of the package 2 and are derived to the outside from the two side surfaces 2A and 2B. Based on the configuration, it is capable of maximizing the size of the semiconductor chip with respect to the size of the package, and it is able to realize the high performance of the element characteristic for the module.

Abstract: A dc-dc controller is provided. The dc-dc controller includes a current sensing pin, a zero-current comparator, a comparison circuit and a threshold adjustment circuit. The current sensing pin is coupled to an output stage to receive a current sensing signal related to the output current. The zero-current comparator is coupled to the current sensing pin, and receives the current sensing signal and a first preset value to provide a zero-current signal. The comparison circuit is coupled to the zero-current comparator and the current sensing pin, and compares the current sensing signal with a second preset value to provide an adjustment signal. The threshold adjustment circuit is coupled to the comparison circuit and the zero-current comparator, and generates the first preset value according to the adjustment signal.

Abstract: Provided is a method of forming a trench gate MOSFET. A hard mask layer is formed on a substrate. The substrate is partially removed by using the hard mask layer as a mask, so as to form a trench in the substrate. A first insulating layer and a first conductive layer are formed in the lower portion of the trench. A sacrificial layer is formed on the side surface of the upper portion of the trench, and the sacrificial layer is connected to the hard mask layer. An interlayer insulating layer is formed on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present. A second insulating layer and a second conductive layer are formed in the upper portion of the trench. A trench gate MOSFET is further provided.

Abstract: A dc-dc converting circuit and a method for controlling the same are provided. The dc-dc converting circuit includes an output stage, a mode detection circuit, a PWM signal generating circuit and a ramp signal generating circuit. The output stage provides an output voltage. The mode detection circuit provides a mode detection signal. The PWM generating circuit provides a time signal to the output stage. When the dc-dc converting circuit enters a continuous conduction mode from a discontinuous conduction mode, the ramp signal generating circuit provides a second ramp signal to the PWM signal generating circuit in a preset time according to the mode detection signal. The ramp signal generating circuit provides a first ramp signal to the PWM signal generating circuit after the preset time. A slope of the second ramp signal is greater than a slope of the first ramp signal.

Abstract: A DC-to-DC controller and a control method thereof are provided. The DC-to-DC controller couples to an output stage, and the output stage provides an output voltage and includes an upper bridge switch and a lower bridge switch. The DC-to-DC controller includes a time signal generating unit and a time signal control circuit. The time signal control circuit couples to the time signal generating unit and receives a preset voltage and the output voltage. During a soft start period, if the output voltage is lower than the preset voltage, after the upper bridge switch is turned off and before the upper bridge switch is turned on again, the time signal control circuit turns off the upper bridge switch and the lower bridge switch for a first preset time and turns on the lower bridge switch for a second preset time.

Abstract: A semiconductor device manufacturing method is disclosed. The semiconductor device manufacturing method includes: a preparation step of preparing a semiconductor wafer; a removal step of removing a thickness part of the semiconductor wafer; and a cutting step of cutting the semiconductor wafer. In the removal step, a rib-shaped portion partially raised on a second main surface of the semiconductor wafer is used as an alignment mark, so that a cutter can align with the semiconductor wafer.