Abstract: A method of defective pixel address detection for image sensor. During the image sensor is tested, a number of defective pixel addresses of the image sensor are stored into a memory element and indexed. Each of the pixels of the image sensor is read in sequence and then compared with the indexed defective pixel address. If the sensor address is equal to the indexed defective pixel address, a defective pixel flag is outputted and then the index is increased by one. If the sensor address is not equal to the defective pixel address, the defective pixel address is compared with an empty signature. After the index is increased or the defective pixel address is not an empty signature, the detection process is continued.

Abstract: The invention provides a method and apparatus for reducing image lag in CMOS active pixel sensors at low light levels by controlling the reset level. By ensuring that the reset level is independent of the preceding signal level, the problem of image lag can be avoided. Always resetting a photodiode to a fixed voltage is a hard reset. The maximum signal swing is limited by the reset level and the column readout amplifier. If the column circuits are not modified, using hard reset can reduce the maximum signal swing. However in dark images only a portion of the full scale is used. Therefore the amplifier gain setting can be used to determine whether to use a hard reset or soft reset. This method and apparatus for using hard or soft reset dependent on signal level improves image quality at low light levels without compromising performance at high illumination.

Abstract: A method of forming a flash memory with a protruded floating gate. A substrate is provided. An isolation area and a plurality of patterned conductive layers are sequentially formed on the substrate. The isolation area protrudes from the upper surface of the substrate to isolate the patterned conductive layers. A photo resist layer is formed on the patterned conductive layer. The present invention also provides a flash memory with a protruded floating gate comprised a substrate, a plurality of protruded floating gates, an insulator, and a control gate.

Abstract: A method of buffer management and task scheduling for two-dimensional data transforming is described. The method includes the steps of reading out old data in a block-by-block pattern and immediately writing in new data in a line-by-line pattern in a buffer using a first mapping scheme. And reading out a following old data in a block-by-block pattern and immediately writing in a following new data in a line-by-line pattern in the buffer using a second mapping scheme. The first and second mapping schemes are interleaved to guarantee output sequences while the buffer is kept full all the time. The buffer thus is maximized, the output flow is continuous and the process loading is smoothed out without loading bursts.

Abstract: A multi-chip semiconductor package structure. The structure includes two chips and two lead frames. The leads on one of the lead frames have inner leads at one end and joint sections at the other end. The joint sections are connected with another lead frame. Both lead frames use a common set of external leads. The two chips and two lead frames are joined together forming a lead-on-chip structure with the two chips facing each other back-to-back. The assembly except the external leads is enclosed by packaging material.

Abstract: An apparatus for solving an edge exclusion problem when polishing a semiconductor wafer includes a rotatable polishing platen with a polishing pad attached to its upper surface. A polishing slurry is deposited on the upper surface of the polishing pad during polishing. Mounted above the polishing pad is a rotatable polishing head for holding a substrate. A non-rotary actuator assembly is coaxially oriented about the outer edge of the polishing head. A ditched ring is removably attached to the bottom surface of the actuator assembly. A multiplicity of conduit grooves are formed in the bottom section of the ditched ring that allows the polishing slurry to travel unimpeded beneath the rotating wafer. A reduced wall thickness at the bottom of the ditched ring is configured to displace wrinkles from the outer edge of the wafer to the outer periphery of the ditched ring. This solves the edge exclusion problem while permitting polishing slurry to pass under the wafer.

Abstract: A method of bad pixel correction for an image sensor. The image sensor has a plurality of rows, and each row includes at least one dark pixel on both ends of the row and valid pixels. The method comprises the steps of inserting a dummy value with a bad pixel flag into a first in first out (FIFO), wherein the dummy value is used for replacing a value of the dark pixel; determining whether a control signal is asserted, wherein the control signal is used for indicating that a current pixel is the valid pixels when the control signal is asserted; writing the values of the valid pixels into the FIFO when the control signal is asserted; determining whether the control signal is deasserted; and inserting a dummy value with a bad pixel flag into the FIFO when the control signal is deasserted.

Abstract: In a method for fabricating a memory cell, a gate stack on a substrate comprises a tunneling dielectric layer, a first conductive layer and a cap layer. Source and drain regions are formed in the substrate adjacent to the gate stack, and spacers are formed on the sidewalls of the gate stack. A plurality of isolation structures are formed through the source/drain regions concurrently to a removal of the cap layer. A second conductive layer is formed over the first conductive layer. By down setting the isolation structures and patterning the second conductive layer over the isolation structures, the patterned second conductive layer is conformal to the profile of the first conductive layer and the spacers by wrapping around the spacers, and extends over the isolation structures. The surface area of the floating thereby formed is increased, which increase the capacitive-coupling ratio.

Abstract: An apparatus for dark level integration comprises a programmable gain amplifier for amplifying signal levels from the pixel. A calibration signal generator for receiving a first calibration signal and a bad pixel signal to generation a second calibration signal, wherein the second calibration signal indicates the existence of the bad pixel. A dark current calibration integrator couples to the programmable gain amplifier and the calibration signal generator for receiving the amplified signal levels from the programmable gain amplifier and the second calibration signal to generate a control signal to the programmable gain amplifier.

Abstract: A method of defective pixel address detection for an image sensor. The method comprises comparing a defective pixel address with a sensor address; outputting a defective pixel flag if the sensor address is equal to the defective pixel address; increasing an index by one; increasing the index by one if the sensor address is larger than the defective pixel address and the index value is not equal to zero, otherwise performing a following step; increasing the index by one if the sensor address is larger than the defective pixel address and the index value is equal to zero and a frame begins, otherwise performing a following step; comparing the defective pixel address with an empty signature; increasing the index by one if the defective pixel address is equal to the empty signature; and returning to the beginning step if the defective pixel address is not equal to the empty signature.

Abstract: The flash memory structure includes a substrate having trenches formed therein, a first dielectric layer and a first conductive layer are stacked on the substrate. Isolations are formed in the trenches and protruding over the surface of the substrate, wherein the first conductive layer is also protruded over the isolations. A second conductive layer is lying the surface of the first conductive layer and a second dielectric layer formed thereon. A third conductive layer is formed on the second dielectric layer. The floating gate is consisted of first conductive layer and the second conductive layer.

Abstract: The present invention includes forming a first conductive layer in a first dielectric layer, followed by forming a second dielectric layer on the first dielectric layer. The second dielectric layer is patterned to form openings on the second dielectric layer, a patterned photoresist is used as a mask to etch holes on the bottom of openings through the second dielectric layer to expose the surface of the first conductive layer 4, and an anti-fuse layer is formed on the second dielectric layer and on a surface of the holes. A photoresist is formed on the anti-fuse layer to expose un-programmable area, followed by plasma etching the anti-fuse layer on the un-programmable area using the photoresist as mask to expose the first conductive layer on the un-programmable area. The photoresist is removed. A second conductive layer is formed on the anti-fuse layer and refilling into the holes.

Abstract: In a method for fabricating a memory cell, a gate stack on a substrate comprises a tunneling dielectric layer, a first conductive layer and a cap layer. Source and drain regions are formed in the substrate adjacent to the gate stack, and spacers are formed on the sidewalls of the gate stack. A plurality of isolation structures are formed through the source/drain regions concurrently to a removal of the cap layer. A second conductive layer is formed over the first conductive layer. By down setting the isolation structures and patterning the second conductive layer over the isolation structures, the patterned second conductive layer is conformal to the profile of the first conductive layer and the spacers by wrapping around the spacers, and extends over the isolation structures. The surface area of the floating thereby formed is increased, which increase the capacitive-coupling ratio.

Abstract: A method of making upper conductive lines in dual damascene process having lower copper conductive lines is disclosed. The processes begin from a substrate having lower copper conductive lines and a via formed in the nitride layer. An oxide layer plays as IMD is then formed on the nitride layer. Next, the oxide layer is patterned to form trenches. Thereafter, a barrier layer is deposited on the resulting exposed surface. An anisotropic etching process is then carried out to form barrier spacers on the sidewall of the trenches. Subsequently, an inert gas bombardment is done to remove a copper oxide layer so as to clean a surface of the via. Next, a conductive layer refilled in the trenches followed by a CMP process is successively performed to form a plurality of upper conductive lines.

Abstract: A process for producing a self-aligned contact comprises the steps of forming leads on a substrate, forming an etching stop layer on the leads by depositing, then forming a sacrificed oxide layer; after the structure of the leads is defined, a spacer is formed on both sides of the structure; a sacrificed oxide layer is formed, allowing the spacer to protrude in the form of horn. Next, a dielectric layer having a flat upper surface is deposited on the substrate and the structure of leads, a contact hole being formed between the leads so as to connect the substrate, a conductive material being filled in the contact hole to form a plug.

Abstract: A method for making a novel structure having borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections on integrated circuits is achieved. An etch-stop layer and a planar insulating layer are formed over the devices on a substrate. Contact openings are etched in the insulating layer to the etch-stop layer and the etch-stop layer is removed over the N− contact areas. An N+ doped polysilicon layer is deposited, and second contact openings are etched in the polysilicon and insulating layers over N+ and P+ contacts on the substrate to the etch-stop layer. The etch-stop layer is selectively removed and a conducting barrier layer and a metal layer are deposited having a second etch-stop layer on the surface. The layers are patterned to form interconnecting lines and concurrently to form polysilicon landing plugs to the N− contacts, while forming metal landing plugs to the N+ and P+ contacts.

Abstract: A capacitor core is formed on a semiconductor device with a first conductive layer in contact with a plug. A mold is formed from a stack of alternately doped and undoped silicon dioxide layers on the sublayer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack. Pattern the silicon dioxide layers in the mold which are alternatingly doped and undoped to form an intercore, capacitor-core-shaping cavity in the stack of silicon dioxide layers reaching down through the stack to be bottom of the stack. Then perform differential etching of the silicon dioxide layers in the mold. Form undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stacks into the cavity to complete the mold.

Abstract: A structure of a stacked gate of a flash memory cell and a method for forming the same is disclosed. A semiconductor substrate having a first conductive gate structure, wherein the first gate conductive structure is disposed in between two neighboring raised shallow trench isolation structures, the dielectric pillar disposed on the sidewall of the first gate conductive structure having a top surface level higher than a top surface of the first gate conductive structure, formed thereon. A conformal conductive layer is formed over the said structure. The conductive layer is patterned to form a second gate conductive structure. The first and the second gate conductive structures forms a floating gate. Next, a thin dielectric layer is formed over the floating gate structure, then another conductive layer is formed over the dielectric layer, and the said conductive layer is patterned to form a control gate.

Abstract: A multi-chip semiconductor package structure. The structure includes two chips and two lead frames. The leads on one of the lead frames have inner leads at one end and joint sections at the other end. The joint sections are connected with another lead frame. Both lead frames use a common set of external leads. The two chips and two lead frames are joined together forming a lead-on-chip structure with the two chips facing each other back-to-back. The assembly except the external leads is enclosed by packaging material.

Abstract: A method for manufacturing a diffusion barrier layer over a substrate having a patterned copper layer. A refractory metal layer is formed on the substrate and a top surface and a sidewall of the patterned copper layer. The refractory metal layer is converted into an implanted layer as a diffusion barrier layer, where gas of N2, O2, or N2O are used for producing implanting ions. A thermal process is performed to stabilize a diffusion barrier quality of the oxygen-containing implantation layer.