Abstract: An improved method for forming a dynamic random access memory (DRAM) capacitor with increased capacitance is disclosed. The method includes forming a polysilicon layer on a substrate, and forming a silicon nitride layer on the polysilicon layer. A photoresist layer is formed on the polysilicon layer to define a storage node area over the substrate surface. After a portion of the silicon nitride layer is removed using the photoresist layer as a mask, a polymer spacer is formed on the sidewalls of the photoresist layer and the silicon nitride layer. The polysilicon layer is removed using the polymer spacer and the photoresist layer as a mask. After the polymer spacer and the photoresist layer are removed, the polysilicon layer is subject to oxidation by using the silicon nitride layer as a mask, thereby forming a polysilicon-oxide layer on the sidewalls and the surface of the polysilicon not covered by the silicon nitride layer.

Abstract: A method for forming a DRAM cell capacitor with increased capacitance includes forming a first dielectric layer and a silicon nitride layer over a substrate. Portions of the nitride layer and the first dielectric layer are then removed. A first doped polysilicon layer is then formed over the nitride layer and filling the first trench. The first doped polysilicon layer is etched back using the nitride layer as an etchstop, thereby forming a polysilicon plug in the first trench. A second dielectric layer is formed on the nitride layer and the polysilicon layer. A second photoresist layer is patterned on the second dielectric layer and reacted with a plasma gas to form a polymer spacer. A portion of the second dielectric layer is removed using the second photoresist layer and polymer spacer as a mask, thereby forming a second trench in the second dielectric layer. A second doped polysilicon layer is formed on the second dielectric layer and in the second trench.

Abstract: The present invention is a method of fabricating a toothed-shape capacitor node in semiconductor DRAM circuit. This invention utilizes dot silicon formed on a nitride layer as an etching mask. The nitride uncovered by the dot silicon is removed. A first layer of poly-oxide is formed using thermal oxidation. The first poly-oxide layer is removed and a second poly-oxide layer is formed using thermal oxidation. The remaining nitride is removed uncovering the polysilicon. The polysilicon is etched to form trenches in the bottom storage of the capacitor. Finally, the second poly-oxide is removed. Thus, a toothed-shape capacitor node is formed in semiconductor circuit.

Abstract: A method of manufacturing a capacitor for use in a DRAM. The method includes forming an isolation layer over a substrate, forming a nitride layer over the isolation layer, forming a hole in the isolation and nitride layers, forming a polysilicon plug in the hole, growing an oxide plug from an upper portion of the polysilicon plug, removing the nitride layer, forming a polysilicon spacer around the oxide plug, and removing the silicon dioxide plug. Additional steps include depositing a dielectric layer onto the polysilicon sidewall and plug, and depositing a third polysilicon layer onto the dielectric layer.

Abstract: The present invention relates to a method of forming a local threshold voltage ion implantation to reduce the junction capacitance in a semiconductor device. A polysilicon layer is formed over the device. A first dielectric layer is formed on the polysilicon layer. Then an opening is formed in the polysilicon layer by using patterning and etching. Subsequently, a second dielectric layer is formed on the first dielectric layer. An etching step is used to formed sidewall spacers on the inner sidewalls of the opening. Then an ion implantation is performed by using said first dielectric layer and sidewall spacers as a mask.

Abstract: A crown-shape capacitor node is formed using a tapered etching process to increase the capacitance of the capacitor. A doped polysilicon layer is deposited over a substrate from which the capacitor node is formed. A tapered trench is formed in a doped polysilicon layer using a mask layer. The mask layer is removed and a dielectric layer is deposited over the doped polysilicon layer and filling the tapered trench. The dielectric layer is then etched back, leaving residual portions in the tapered trench. The doped polysilicon layer is then etched using the dielectric material in the tapered trench as an etching mask. The resulting capacitor node has tapered sidewalls, which increases the surface area of the capacitor node, thereby increasing the capacitor's capacitance. The mask layer can be formed so that the tapered etching process forms the capacitor node with either tapered exterior sidewalls or a tapered trench.

Abstract: The present invention provides a method of manufacturing a fence shaped capacitor for a DRAM which begins by providing a substrate including a field effect transistor having a transfer gate with nitride sidewall spacers. Next, a first insulation layer, a first polysilicon layer and a second insulation layer are formed over the transistor. A patterning step is used to define first openings in the second insulation layer over the source of the transistor. First polysilicon sidewall spacers (e.g., fences) are formed on the sidewalls of the first opening thus defining a second opening. Using the first spacers and the spacers on the transfer gates, the first insulation layer is etched to expose the source and thereby forming a node contact opening. A bottom storage electrode is formed covering the first spacers (e.g., fences) and the sidewall of the node contact opening. A dielectric layer and top plate electrode are formed over the bottom storage electrode.

Abstract: A new combination container for wafers, and a retainer element to prevent movement of the wafers in the container, is described. The container has a body member with a circular base with a flat upper surface for supporting stacked wafers, and an upright arcuate member on the base that is adapted to encircle approximately 180.degree. of the stack of wafers. An enclosure member with a top and a cylindrical wall mates with the body member to enclose the upright member and a stack of wafers. A suitable means is provided to secure the body member and enclosure member together in sealed relationship. The wafer carrier of the invention improves the handling and storage of large diameter semiconductor wafers, is easier to load and unload, and can be opened and closed with a minimum of effort and a reduced probability of damaging the wafers.

Abstract: A process has been developed that allows small diameter contact holes to be filled with chemical vapor deposited tungsten, without tungsten peeling from the sides of the contact hole. The process consists of initially depositing an adhesive layer of titanium in the contact hole, followed by a rapid thermal anneal cycle, in an ammonia ambient, for purposes of creating a thin, uniform, barrier layer of titanium nitride. The titanium nitride protects the underlying titanium adhesion layer from the by-products introduced during the tungsten deposition, specifically the evolution of fluorine ions resulting from the decomposition of tungsten hexafluoride.

Abstract: A DRAM capacitor is formed over a device with FOX regions and device areas with S/D regions. Form a planarization silicon oxide layer over the device and FOX areas covered with an etch stop layer and a first portion of a first capacitor plate over the planarization layer, a contact opening to the S/D areas by etching through the first capacitor layer and layers down to a S/D region. Form a second portion of a first plate over the device and through the contact opening into electrical and mechanical contact with one of the S/D areas, the second portion has exposed sidewalls and a top surface extending above the surface of the device. Form sacrificial spacers adjacent to the sidewalls of the second portion. Deposit a third portion of the first plate over the device. Etch back the third portion down to the etch stop layer to expose the sacrificial structure and remove the sacrificial structure. Form an interconductor dielectric layer and an upper capacitor plate extending between the second and third portions.

Abstract: A process for fabricating stacked capacitor DRAM devices has been developed in which self aligned storage node contact structures, as well as bit line contact structures, are featured. A split polysilicon process has also been used to allow maskless source and drain ion implantation processing to be realized, thus reducing the number of photolithographic steps. A dual dielectric, interlevel insulator, is used to eliminate leakage between metal levels.

Abstract: The present invention provides a method of simultaneously forming CMOS DRAM cells, CMOS devices, and vertical bipolar transistors on the same chip. The invention utilities a CMOS DRAM process to simultaneously fabricate a vertical bipolar transistor and uses only one additional mask (a base implant mask) compared to forming the DRAM cell alone. Also, to reduce the bipolar collector plug resistance, the process uses a tungsten-plug module where the collector is formed within a field oxide region near the base.

Abstract: A method is provided for fabricating a single crown electrode for a capacitor for semiconductor memory devices. A conductive layer is formed over a multi-layer gate and insulation structure. The conductive layer includes a portion extending through a contact hole to thereby electrically connect the conductive layer with an active region of a transistor formed in the substrate Next, a novel groove is etched in the conductive layer between adjacent memory cells. Sidewall spacers are formed on the groove. The conductive layer is anisotropically etched using the spacers as an etching mask, thereby forming a plurality of electrodes having upright portions. The etching exposes the first insulation layer in the area under the grooves, but leaves a thickness of the base conductive layer to form the bottom of the electrode. The spacers then are removed and a conformal dielectric layer is formed over the surface. Lastly, a top plate electrode is formed over the conformal dielectric layer.

Abstract: A method for optimizing the connection between active device regions in silicon, to overlying metallization levels, has been developed. A polysilicon contact plug process, consuming less area then conventional contacts, has been created. The highlight of this process is the complete conversion of residual polysilicon, in all areas except in the contact hole, to thermal oxide. The thermal oxide is then selectively removed, resulting in a polysilicon contact plug structure.