Abstract: A method of manufacturing a double gate oxide layer. A substrate has trenches that divide the substrate into a memory circuit region and a logic circuit region. A dielectric layer is formed on the substrate to fill the trenches. The dielectric layer of the logic region is removed, thereby exposing the substrate. An ion implantation step is performed on the substrate of the logic circuit region using a reverse tone mask. A conformal barrier layer is formed over the substrate. A spin-on layer is formed over the barrier layer. A chemical mechanical polishing step is performed to remove the in-on layer, the barrier layer, and dielectric layer outside the trenches, thereby exposing the substrate. A thermal oxidation step is performed to form a double gate oxide layer that is thicker in the logic circuit region than it is in the memory circuit region.

Abstract: The invention provides a method of manufacturing a semiconductor device comprising the following steps. A silicon substrate is provided. A first oxidation-resistant layer is formed on the silicon substrate. The first oxidation-resistant layer and the silicon substrate are formed to form a trench. A second oxidation-resistant layer if formed on the first oxidation-resistant layer and inside the trench. A portion of the second oxidation-resistant layer is removed to form a spacer on sidewalls of the trench. A portion of the exposed silicon substrate on bottom of the trench is performed by directional etching to expose a portion of the sidewalls of the trench. A thermal oxidation step is performed on the exposed portion of the sidewall of the trench. The second spacer is removed and a dielectric layer is formed over the substrate to fill in the trench.

Abstract: An ESD (electrostatic discharge) protection circuit employs a field oxide region between the drain region and the source region to break a surface channel between the drain region and the source region. As a result, the whole ESD current is discharged via the substrate to the ground by using a gate-modulated field-oxide device, and the potential endurance of ESD device can be improved. Additionally, the invention utilizes circuit technology to detect an ESD signal so that the response speed can be increased. Furthermore, the invention can maintain a deep current path due to the gate-modulated field-oxide device for improving its ESD robustness and decreasing the device size effectively and achieving a better ESD protection efficiency.

Abstract: A method of manufacturing semiconductor devices. An alignment mark is formed in any one of the dies in a substrate. A waiting-for-patterning layer is formed over the dies. A negative photoresist layer is formed over the waiting-for-patterning layer. A first exposure is carried out so that a plurality of first exposed regions is formed in all the dies of the chip. A second exposure is carried out to form a second exposed region. The second exposed region overlaps with the first exposed region and the unexposed region above the alignment mark and the overlapping region covers the alignment mark region. A photoresist development is conducted to remove the negative photoresist in the unexposed regions. Using the negative photoresist as a mask, a portion of the waiting-for-patterning layer is removed to form a pattern on the waiting-for-patterning layer. The negative photoresist layer is removed.

Abstract: A method is disclosed for fabricating a semiconductor device structure which include a thin foot charge drain beneath the device on a silicon substrate. The structures retain high speed operation of SOI devices. In various embodiments, the invention includes forming a first diffusion-barrier layer on a semiconductor substrate, patterning the said first diffusion-barrier layer and the said silicon substrate to certain depth to form a trench, forming a second diffusion-barrier layer and patterning the said second diffusion-barrier layer to form a first spacer on the sidewall of the trench. Performing a directional etching to expose a portion of the sidewall of the trench. Introducing dopants into the said exposed sidewall to form a doped regions near the sidewall. Performing an isotropic etching using halogen gas plasma.

Abstract: A fabrication method for forming asymmetric wells of a DRAM cell, and more particularly to a fabrication method for producing a transistor that is capable of reducing body effect, gate-swing and junction leakage current so as to enhance the reliability of a DRAM device. After doped regions used for source/drain are formed in a substrate, a local well and an anti-punchthrough pocket are then formed under the doped region to be used as drains in order to prevent short channel effect. Because the local well and the anti-punchthrough pocket do not extend to the doped region that is used as a source, the DRAM cell's ability for charge retention therefore can be kept at the same time.

Abstract: A method is directed to form a semiconductor device with silicide formed by a metal layer associated with a deposited silicon layer by providing a substrate. A field oxide layer is formed on a substrate to define an active region. A gate structure is formed on the active region, where the gate structure has a gate oxide layer, a gate layer, and a cap layer on the gate layer. The field oxide layer has a height substantially equal to the cap layer. A spacer is formed on a sidewall of the gate structure. The cap layer is removed to expose the gate layer, whereby a trench is formed. A silicon layer is deposited over the substrate. A refractory metal layer is deposited on the silicon layer. A silicide layer is formed by performing a thermal process to trigger a reaction between the silicon layer and the metal layer. The silicide layer is polished by CMP process using the field oxide layer as a polishing stop.

Abstract: A method of manufacturing a shallow trench isolation structure. A pad oxide layer is formed on a substrate, and a mask layer is formed on the pad oxide layer. Next, using a photoresist having opening patterns as a mask, the mask layer and the pad oxide layer are etched, and a trench is formed within the substrate. Thereafter, the photoresist is laterally etched, thereby causing the photoresist openings to enlarge. Next, the mask layer exposed by the openings is etched, thereby forming a wide opening in the mask layer. Subsequently, the photoresist layer is removed, and the insulation layer is formed on the upper portion of the mask, within the wide opening and inside trench. Next, using the mask layer as the polishing stop layer, a chemical mechanical polish procedure is performed, thereby removing a portion of the insulation layer, exposing the mask layer and an even surface is achieved.

Abstract: The method of the invention contains providing a substrate, which has several conductive structures formed thereon. The conductive structure has a cap layer on top. A dielectric layer is formed over the substrate and the conductive structures. The dielectric layer is patterned to form an opening between the conductive structures to expose the substrate, the sidewalls of the conductive structures, and a portion of top surface of the conductive structures. A conductive plug fills the opening. A dielectric block formed on the conductive plug. A conductive spacer is formed on the sidewalls of the dielectric block, having electrical contact to the conductive plug. The dielectric block is removed to expose the conductive plug. A hemi-spherical grain (HSG) layer is formed on the topographic surface of the substrate. A dielectric spacer is formed on sidewall of the conductive spacer to cover a portion of the HSG layer.

Abstract: A method for fabricating a transistor having a T-shape gate. A substrate having a sacrificial layer, a metal layer and an insulating layer in turn formed thereon is provided. A photoresist layer is formed over the insulating layer, and then using the patterned photoresist layer as a mask a portion of the insulating layer and the metal layer are removed to formed the first gate window. The photoresist layer is then further laterally removed, and using the remained photoresist as a mask the remained insulating layer is further laterally removed to form a second gate window. Therefore, a T-shape gate window is formed and a T-shape gate structure can be formed within the T-shape gate window.

Abstract: A structure of manufacture of a semiconductor die on a lead-on-chip (LOC) packaging using a flexible copper plated tape and a standard lead frame is disclosed. A semiconductor die with bonding pads in the center is interconnected to a flexible copper plated tape by copper trace, solder bumps, or gold bump. The flexible copper plated tape is then placed on top of and attached to a standard lead frame. The configuration of a flexible copper plated tape, such material includes polymide tape, matches the configuration of a lead frame that allows the use of a standard outer lead frame. The configuration of a polymide tape provides greater flexibility in the placement of bonding pads anywhere on a semiconductor die without limiting the bonding pads to be placed in the center of a semiconductor die.

Abstract: A fabrication process for a lower electrode of a memory capacitor, which process is performed on a substrate already having a first insulating layer formed thereon. First, a self-aligned contact opening is formed in a first insulating layer. The self-aligned contact opening exposes a conducting area on the substrate. A conformal first conductive layer is formed on the first insulating layer and in the self-aligned contact opening, the bottom of which functions as a contact. Then, the self-aligned contact opening is filled with a second insulating layer. The first conductive layer is back etched so as to remove completely the first conductive layer that is outside the self-aligned contact opening, and to remove to a certain depth the first conductive layer that is inside the self-aligned contact opening. A second conductive layer is then formed on the sidewalls of the first and second insulating layers that are located inside the self-aligned contact opening.

Abstract: The present invention provides a method to form a dishing-free insulator in trench isolation without repeated formations of silicon sidewall spacers and thermal oxidation of the silicon sidewall spacers. Using Ion-Metal Plasma (IMP) process to deposit silicon film directionally in the trenchs of the substrate is the key point of the present invention.

Abstract: A method for fabricating an SOI semiconductor device with reduced floating body effects and a simplified method of fabrication. In the invention, a N-type doped dielectric layer or P-type doped dielectric layer is used to be driven into the semiconductor layer to form source/drain regions of field effect transistors of CMOS and conductive regions. For fabricating a NMOS transistor and a PMOS transistor of the CMOS device, the invention provides a method which an ion implantation process and a photo mask are omitted, by which the method will decrease the complexity of the fabrication process and the cost thereof.

Abstract: A method for manufacturing a diffusion barrier layer over a substrate having a patterned copper layer. A refractory metal layer or a nitride layer of refractor metal is formed on the substrate and a top surface and a sidewall of the patterned copper layer. The refractory metal layer or the nitride layer of refractor metal is converted by HDP treatment into an implanted layer as a diffusion barrier layer, where gas of N2, O2, NH3, NO2; or N2O are used for producing implanting ions. A thermal process is performed stabilize a diffusion barrier quality of the oxygen-containing implantation layer.

Abstract: A process for forming a composite structure, comprised of an overlying titanium nitride barrier layer, and an underlying titanium disilicide layer, located on a portion of a conductive region in a semiconductor substrate exposed at the bottom of a high aspect ratio contact hole, has been developed. A first iteration of this invention entails the deposition of a titanium ion layer, via an anisotropic, ion metal plasma (IMP), procedure, on the exposed portion of the conductive region, as well as on the top surface of the insulator layer in which the high aspect ratio contact hole was formed in. A first anneal cycle results in the formation of a titanium disilicide layer on the conductive region, leaving an unreacted titanium ion layer on the surface of the insulator layer. After removal of unreacted titanium, a second anneal cycle is performed in a nitrogen containing ambient, converting a top portion of the titanium disilicide layer to a titanium nitride barrier layer.

Abstract: A method for manufacturing a shallow trench isolation structure. A pad oxide layer and a mask layer are formed over a substrate. Portions of the mask layer, the pad layer and substrate are removed forming a trench. Oxidation of the substrate within the trench forms a linear oxide layer. The substrate at the bottom of the trench is exposed by removing a portion of the linear oxide layer at the bottom of the trench. A polysilicon layer, deposited completely over the mask, fills the trench as well. The polysilicon layer on the mask layer and outside the trench is removed, leaving polysilicon within the trench, which forms a polysilicon plug. A thin conformal barrier layer is formed over the substrate. An insulator layer is deposited above the barrier layer. The isolation layer and barrier layer on top of the mask as well as outside the trench are removed using a chemical mechanical polishing method. The mask is removed.

Abstract: A sense amplifier (SA) stage includes a single SA used to selectively sense signals from both directions in a datapath. The SA is connected to detect the differential signal present at a pair of sense nodes on the datapath. A first pair of switches is inserted in the datapath between the sense nodes and a first transfer port (FTP). A first equalizer is connected to the differential lines at points between the first pair of switches and the FTP. A second pair of switches is inserted in the datapath between the sense nodes and a second transfer port (STP), with a second equalizer connected to the differential lines between the second pair of switches and the STP. Before transferring data from the FTP to the STP, the first equalizer is turned on while the first pair of switches is turned off. While the data is being developed at the FTP, the first equalizer is turned off, the first pair of switches is turned on, the second pair of switches is off, and the second equalizer is on.

Abstract: A method for fabricating a transistor having a T-shape gate. A substrate having a sacrificial layer, a metal layer and an insulating layer in turn formed thereon is provided. A masking layer is formed over the insulating layer, and then using the patterned masking layer as a mask a portion of the insulating layer and the metal layer are removed to formed the first gate window. The masking layer is then further laterally removed, and using the remained masking as a mask the remained insulating layer is further laterally removed to form a second gate window. Therefore, a T-shape gate window is formed and a T-shape gate structure can be formed within the T-shape gate window.

Abstract: A method of fabricating a shallow trench isolation. A trench is formed in a substrate. An insulation plug is formed to fill the trench. The trench has an exposed upper portion above the substrate. A silicon spacer is formed on a side wall of the exposed upper portion. The silicon spacer is oxidized into a silicon oxide spacer.