Abstract: An apparatus including a microprocessor, a system memory, and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program. The secure application program is executed in a secure execution mode. The microprocessor has secure watchdog logic that monitors environmental attributes corresponding to the microprocessor and to the secure application program, and that transfers program control to one of a plurality of event handlers within the secure application program. The system memory has non-secure application programs stored therein. The secure non-volatile memory is coupled to the microprocessor via a private bus.

Abstract: An online upgrade system/method for a memory. The system includes a host and an electronic device. An application is executed by the host and contains parameter records for different memory model types. The electronic device includes a memory and a device controller. The application distinguishes the model type of the memory equipped in the electronic device, and according to the model type of the memory, the application provides the device controller with the parameter record corresponding thereto and thereby the application upgrades the contents of the memory through the device controller.

Abstract: A method for a 3D computer graphics shading process compiler, utilized to generate hardware machine code corresponding to a script is disclosed. The method includes the following steps. Operation mapping code indicating an operation of the script, and argument mapping code indicating an argument associated with the operation is provided. The hardware machine code is generated by performing a bitwise OR operation to the operation mapping code and the argument mapping code.

Abstract: A power management method for a host computer, which is coupled to a USB hub, is provided. It prevents the USB hub from entering into a suspend mode while the host computer stays in a host active state. The method includes the following steps: a filter driver is loaded. When detecting a specified event, the filter driver issues a device sleep IRP request to control the USB hub enter into a suspend mode. Wherein the specified event represents that the host computer enters into a host sleep state.

Abstract: A microprocessor invokes microcode in response to encountering a repeat load string instruction. The microcode includes a series of guaranteed prefetch (GPREFETCH) instructions to fetch into a cache memory of the microprocessor a series of cache lines implicated by a string of data bytes specified by the instruction. A memory subsystem of the microprocessor guarantees within architectural limits that the cache line specified by each GPREFETCH instruction will be fetched into the cache. The memory subsystem completes each GPREFETCH instruction once it determines that no conditions exist that would prevent fetching the cache line specified by the GPREFETCH instruction and once it allocates a fill queue buffer to receive the cache line. A retire unit frees a reorder buffer entry allocated to each GPREFETCH instruction in response to completion of the GPREFETCH instruction regardless of whether the cache line specified by the GPREFETCH instruction has been fetched into the cache.

Abstract: Methods and systems for performing control of flow in a graphics processor architecture are provided. For example, in at least one embodiment, a computing system includes a memory storing a plurality of instructions and a graphics processing unit. The graphics processing unit is configured to process the instructions according to a multi-stage scalar pipeline and store condition code values in the branch control stack. The graphics processing unit is further configured to process branch instructions using condition code values stored in the condition register at the top of the branch control stack.

Abstract: A microprocessor includes an MSR and fuses. The microprocessor encounters an instruction requesting access to the MSR and specifying the MSR address, performs a function of the specified MSR address and a value read from the fuses to generate a first result, encrypts the first result with a secret key to generate a second result, compares the second result with an instruction-specified password, and allows the instruction to access the MSR if the second result matches the password and otherwise denies access MSR. Manufacturing subsequent instances of the microprocessor with a different fuse value effectively revokes the password. Alternatively, a control register of the microprocessor may be written by system software to override the fuse value and thereby revoke the password. The function may be XOR or concatenation, the encryption may be AES, and the secret key is externally invisible.

Abstract: A microprocessor includes hardware registers that instantiate the IA-32 Architecture EDX and EAX GPRs and hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs. The microprocessor associates with each of the R8-R15 GPRs a respective unique MSR address. In response to an IA-32 Architecture RDMSR instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor reads the contents of the hardware register that instantiates the specified one of the R8-R15 GPRs into the hardware registers that instantiate the EDX:EAX registers. In response to an IA-32 Architecture WRMSR instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor writes into the hardware register that instantiates the specified one of the R8-R15 GPRs the contents of the hardware registers that instantiate the EDX:EAX registers. The microprocessor does so even when operating in non-64-modes.

Abstract: A microprocessor includes hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs. The microprocessor associates with each of the R8-R15 GPRs a respective unique MSR address. The microprocessor also includes hardware registers that instantiate the ARM Architecture GPRs. In response to an ARM MRRC instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor reads the contents of the hardware register that instantiates the specified one of the R8-R15 GPRs into the hardware registers that instantiate two of the ARM GPRs registers. In response to an ARM MCRR instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor writes into the hardware register that instantiates the specified one of the R8-R15 GPRs the contents of the hardware registers that instantiate two of the ARM Architecture GPRs registers. The hardware registers may be shared by the two Architectures.

Abstract: A capacitor structure including a dielectric material layer and at least two metal layers is provided. The metal layers are disposed at intervals in the dielectric material layer. Each of the metal layers includes a zigzaging electrode, a first finger-shaped electrode and a second finger-shaped electrode. The zigzaging electrode forms a plurality of first concave parts disposed at one side of the zigzaging electrode and a plurality of second concave parts disposed at the other side of the zigzaging electrode. The first finger-shaped electrode includes a plurality of first extension parts. The first extension parts are respectively disposed in the first concave parts. The second finger-shaped electrode includes a plurality of second extension parts. The second extension parts are respectively disposed in the second concave parts. The zigzaging electrode in each of the metal layers is electrically coupled to the first and second finger-shaped electrodes of adjacent metal layers.

Abstract: A signal generation device is provided to generate an output signal with constant frequency. The signal generation device includes a frequency-control circuit and a voltage-controlled delay line. The frequency-control circuit is arranged to charge/discharge a voltage-control node according to a comparison result signal. The voltage-controlled delay line is arranged to generate a control signal according to the comparison result signal and a control voltage of the voltage-control node to control the output signal. A frequency of the control signal is modulated by the voltage-controlled delay line according to the control voltage of the voltage-control node. The comparison result signal is generated according to a difference between a reference voltage and a voltage level of the output signal.

Abstract: A level shifter, converting an input signal into an output signal for level shifting, including a leakage blocking circuit having cascaded P-channel transistors and one N-channel transistor. The P-channel transistor at a beginning stage provides a gate for receiving the input signal and a source coupled to a gate of the P-channel transistor at a secondary stage. At intermediate stages, each P-channel transistor provides a source coupled to a gate of the subsequently cascaded P-channel transistor. At a final stage, the P-channel transistor provides a source coupled to a voltage source and a drain coupled to an output terminal of the leakage blocking circuit for the outputting of the output signal. The N-channel transistor has a gate which is coupled to receive the input signal as well, a source coupled to a common voltage, and a drain coupled to the output terminal of the leakage blocking circuit.

Abstract: The present invention is directed to a universal serial bus (USB) transaction translator and a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, wherein the counting value of the SOF counter is compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves the predefined value or is greater than the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time.

Abstract: A computing system includes a microprocessor that receives values for configuring operating modes thereof. A device driver monitors which software applications currently running on the microprocessor are in a predetermined list and responsively dynamically writes the values to the microprocessor to configure its operating modes. Examples of the operating modes the device driver may configure relate to the following: data prefetching; branch prediction; instruction cache eviction; instruction execution suspension; sizes of cache memories, reorder buffer, store/load/fill queues; hashing algorithms related to data forwarding and branch target address cache indexing; number of instruction translation, formatting, and issuing per clock cycle; load delay mechanism; speculative page tablewalks; instruction merging; out-of-order execution extent; caching of non-temporal hinted data; and serial or parallel access of an L2 cache and processor bus in response to an instruction cache miss.

Abstract: Systems and methods for improving throughput of a graphics processing unit are disclosed. In one embodiment, a system includes a multithreaded execution unit capable of processing requests to access a constant cache, a vertex attribute cache, at least one common register file, and an execution unit data path substantially simultaneously.

Abstract: Determining and simultaneously using a base station coupled to a mobile device, the base station comprising a detector for receiving a first identification signal corresponding to a first module and a second identification signal corresponding to a second module from the mobile device. A transmitter for sending a plurality of signals to the mobile device, said plurality of signals is configured to set up communication between the mobile device and the base station. A receiver for receiving a plurality of parameters for determining whether the second module is able to attach to the base station; and a processor for connecting the first and second module in the mobile device to the base station simultaneously in response to a plurality of slots by time multiplexing and the plurality of parameters when the second module is acceptable by the base station, wherein said plurality of slots are determined by the base station.

Abstract: A microprocessor includes a first instruction translator that translates an instruction of an instruction set architecture of a microprocessor. The instruction may specify a first form that writes its result to a destination register or a second form that writes its result to memory. The first instruction translator generates, in response to encountering an instance of the instruction, an indication of whether the instance is of the first form or the second form. A microcode memory stores a tail instruction as part of a microcode routine invoked in response to encountering the instance of the instruction. A second instruction translator receives the tail instruction from the microcode memory and the indication and responsively generates a first micro-operation that writes the result to the destination register if the indication specifies the first form or a second micro-operation that completes a write of the result to memory if the indication specifies the second form.

Abstract: An integrated circuit for accessing a universal serial bus (USB) device via a USB 3.0 receptacle is provided. The integrated circuit includes a plurality of pins and a controlling unit. The pins include a first group for coupling to a first pair of differential pins of the USB receptacle, a second group for coupling to a second pair of differential pins of the USB receptacle, a third group for coupling to a third pair of differential pins to the USB receptacle, a ground pin, a first and second power pins. The second group is disposed between the first and third groups. The controlling unit controls the plurality of pins to receive or transmit the USB 2.0 or USB 3.0 signals.

Abstract: A differential signal pair transmission structure adapted to a wiring board and including a first signal path and a second signal path is provided. The first signal path includes a first upper trace, a first lower trace and a first conductive through via. The second signal path includes a second upper trace, a second lower trace and a second conductive through via. A portion of the first signal path and a portion of the second signal path overlaps in the normal projection onto the upper or lower surface of the wiring board. Normal projections of the first and the second signal path projecting onto the upper surface of the wiring board are substantially symmetric with respect to a line which is perpendicular to a segment connecting normal projections of axes of the first and the second through via onto the upper surface and passes through the midpoint of the segment.

Abstract: A process for fabricating process a circuit substrate having a base layer, a first patterned conductive layer, a dielectric layer, a conductive block and a second patterned conductive layer. The first patterned conductive layer is disposed on the base layer and has a first pad. The dielectric layer is disposed on the base layer and covers the first patterned conductive layer, wherein the dielectric layer has an opening and the first pad is exposed by the opening. The conductive block is disposed in the opening and covers the first pad. The second patterned conductive layer is disposed on a surface of the dielectric layer and has a second pad, wherein the second pad and the conductive block are integrally formed.