Abstract: An apparatus that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network and a synchronous receiver disposed within a receiving device. The resistor network is configured to provide a ratio signal that indicates an amount to delay a data bit signal associated with a data group, where the data bit signal is transmitted by a transmitting device along with a data strobe signal. The synchronous receiver receives the data bit and the data strobe signals, and includes a delay-locked loop (DLL). The DLL is coupled to the ratio signal, and is configured generate a delayed data bit signal, where the DLL adds the amount of delay to the data bit signal to generate the delayed data bit signal, and where the delayed bit signal is delayed relative to the data strobe signal by the amount, thus allowing for proper reception of the data bit signal.

Abstract: An image processing system and an image processing method are provided. The image processing method includes following steps. Transformation matrixes between color channel images are obtained according to feature points in the color channel images. A transformation matrix having the minimum distortion is selected to determine a shift datum color channel image. The other color channel images are transformed according to the transformation matrixes corresponding to the shift datum color channel image. The shift datum color channel image and the transformed color channel images are combined to obtain a shift calibrated image. Thereby, the dispersion problem is resolved.

Abstract: A method for encrypting a program for subsequent execution by a microprocessor configured to decrypt and execute the encrypted program includes receiving an object file specifying an unencrypted program that includes conventional branch instructions whose target address may be determined pre-run time. The method also includes analyzing the program to obtain chunk information that divides the program into a sequence of chunks each comprising a sequence of instructions and that includes encryption key data associated with each of the chunks. The encryption key data associated with each of the chunks is distinct. The method also includes replacing each of the conventional branch instructions that specifies a target address that is within a different chunk than the chunk in which the conventional branch instruction resides with a branch and switch key instruction. The method also includes encrypting the program based on the chunk information.

Abstract: A microprocessor includes an architected register having a bit. The microprocessor sets the bit. The microprocessor also includes a fetch unit that fetches encrypted instructions from an instruction cache and decrypts them prior to executing them, in response to the microprocessor setting the bit. The microprocessor saves the value of the bit to a stack in memory and then clears the bit, in response to receiving an interrupt. The fetch unit fetches unencrypted instructions from the instruction cache and executes them without decrypting them, after the microprocessor clears the bit. The microprocessor restores the saved value from the stack in memory to the bit in the architected register, in response to executing a return from interrupt instruction. The fetch unit resumes fetching and decrypting the encrypted instructions, in response to determining that the restored value of the bit is set.

Abstract: A microprocessor is provided with a method for decrypting encrypted instruction data into plain text instruction data and securely executing the same. The microprocessor includes a master key register file comprising a plurality of master keys. Selection logic circuitry in the microprocessor selects a combination of at least two of the plurality of master keys. Key expansion circuitry in the microprocessor performs mathematical operations on the selected master keys to generate a decryption key having a long effective key length. Instruction decryption circuitry performs an efficient mathematical operation on the encrypted instruction data and the decryption key to decrypt the encrypted instruction data into plain text instruction data.

Abstract: An apparatus for generating a decryption key for use to decrypt a block of encrypted instruction data being fetched from an instruction cache in a microprocessor at a fetch address includes a first multiplexer that selects a first key value from a plurality of key values based on a first portion of the fetch address. A second multiplexer selects a second key value from the plurality of key values based on the first portion of the fetch address. A rotater rotates the first key value based on a second portion of the fetch address. An arithmetic unit selectively adds or subtracts the rotated first key value to or from the second key value based on a third portion of the fetch address to generate the decryption key.

Abstract: A natural language dialogue system and a method capable of correcting a speech response are provided. The method includes following steps. A first speech input is received. At least one keyword included in the first speech input is parsed to obtain a candidate list having at least one report answers. One of the report answers is selected from the candidate list as a first report answer, and a first speech response is output according to the first report answer. A second speech input is received and parsed to determine whether the first report answer is correct. If the first report answer is incorrect, another report answer other than the first report answer is selected from the candidate list as a second report answer. According to the second report answer, a second speech response is output.

Abstract: A natural language dialogue method and a natural language dialogue system are provided. In the method, a first speech input is received and parsed to generate at least one keyword included in the first speech input, so that a candidate list including at least one report answer is obtained. According to a properties database, one report answer is selected from the candidate list, and a first speech response is output according to the report answer. Other speech inputs are received, and a user's preference data is captured from the speech inputs. The user's preference data is stored in the properties database.

Abstract: A search method, a search system, and a natural language comprehension system are provided. The search system includes a structured database and a search engine. The structured database stores a plurality of records, each of which has a title field and a content field. The title field includes at least one sub-field, and each sub-field includes an indication field and a value field. The indication field stores indication data, the value field stores value data, and the content field stores detailed content data. The search engine conducts a full-text search to the records in the structured database according to a keyword derived from a user's request formation, and a search result is transmitted to a knowledge comprehension assistance module, so as to recognize the user's intention. After the user's intention is recognized, information associated with the recognized user's intention is transmitted back to the user.

Abstract: An operating system switching method is provided. The operating system switching method is for a computer system comprising a control unit, a memory unit, and a storage unit, wherein the storage unit comprises a first operating system and a second operating system. The steps of the method include: loading the first operating system and the second operating system into a first memory space and a second memory space of the memory unit, respectively, and setting the first memory space and the second memory space to a working state and a standby state, respectively; and performing a first switching of the operating systems, and setting the first memory space and the second memory space to the standby state and the working state.

Abstract: A USB hub and a method thereof. The USB hub supplies power to a USB device, is connected between the USB device and a USB host under a working power state, and comprises an upstream port, a downstream port, a power port, and a controller. The upstream port is coupled to the USB host. The downstream port is coupled to the USB device. The power port is coupled to a power source. The controller is coupled to the upstream port, the downstream port, and the power port, and determines whether the USB host has left the working power state, and determines whether the USB device is electrically chargeable, when the USB host has left the working power state. The downstream port provides power to the USB device from the power source when the USB device is electrically chargeable.

Abstract: Systems and methods for sharing a physical cache among one or more clients in a stream data processing pipeline are described. One embodiment is directed to a system for sharing caches between two or more clients. The system comprises a physical cache memory having a memory portion accessed through a cache index. The system further comprises at least two virtual cache spaces mapping to the memory portion, each of the virtual cache spaces has an active window which has a different size than the memory portion. Further, the system comprises at least one virtual cache controller configured to perform a hit-miss test on the active window of the virtual cache space in response to a request from one of the clients for accessing the physical cache memory. Furthermore, data is accessed from the corresponding location of the memory portion when the hit-miss test of the cache index returns a hit.

Abstract: An apparatus providing for a secure execution environment is presented. The apparatus includes a microprocessor and a secure non-volatile memory. The a microprocessor is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus. The microprocessor has a plurality of timers which are visible and accessible only by the secure application program when executing in a secure execution mode. The secure non-volatile memory is coupled to the microprocessor via a private bus and is configured to store the secure application program in encrypted form. Transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus, the system memory, and corresponding system bus resources within the microprocessor.

Abstract: A data prefetcher in a microprocessor having a cache memory receives memory accesses each to an address within a memory block. The access addresses are non-monotonically increasing or decreasing as a function of time. As the accesses are received, the prefetcher maintains a largest address and a smallest address of the accesses and counts of changes to the largest and smallest addresses and maintains a history of recently accessed cache lines implicated by the access addresses within the memory block. The prefetcher also determines a predominant access direction based on the counts and determines a predominant access pattern based on the history. The prefetcher also prefetches into the cache memory, in the predominant access direction according to the predominant access pattern, cache lines of the memory block which the history indicates have not been recently accessed.

Abstract: A method for debugging a multi-core microprocessor includes causing the microprocessor to perform an actual execution of instructions and obtaining from the microprocessor heartbeat information that specifies an actual execution sequence of the instructions by the plurality of cores relative to one another, commanding a corresponding plurality of instances of a software functional model of the cores to execute the instructions according to the actual execution sequence specified by the heartbeat information to generate simulated results of the execution of the instructions, and comparing the simulated results with actual results of the execution of the instructions to determine whether they match. Each core outputs an instruction execution indicator indicating the number of instructions executed by the core each core clock. A heartbeat generator generates a heartbeat indicator for each core on an external bus that indicates the number of instructions executed by each core during each external bus clock cycle.

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, and a delay-locked loop (DLL). The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to delay a data bit signal associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The DLL is coupled to the ratio bus, and is configured generate a delayed data bit signal, where the DLL adds the amount of delay to the data bit signal to generate the delayed data bit signal.

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a composite delay element, and delay-locked loops (DLLs). The resistor network is configured to provide a ratio signal that indicates an amount to delay data bit signals associated with a data group. The composite delay element is configured to equalize delay paths within a receiving device, where the delay paths correspond to a data strobe signal that is received from a transmitting device. The receiving device and resistor network are coupled to a motherboard. The ratio signal enters said receiving device through an external pin. The DLLs are coupled to the ratio signal and disposed within the receiving device, and are configured to generate delayed data bit signals, where the DLLs add the amount of delay to the data bit signals to generate the delayed data bit signals.

Abstract: An apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, a core clocks generator, and a synchronous strobe driver. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to advance a synchronous data strobe associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The core clocks generator is coupled to the ratio bus and is configured to advance a data strobe clock by the amount. The synchronous strobe driver is configured to receive the data strobe clock, and is configured to employ the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the amount.

Abstract: A lead arrangement is provided for an electric connector. The lead arrangement includes a first lead lane that includes a pair of first differential signal leads, a pair of second differential signal leads and a first ground lead between the two pairs of differential signal leads. Each of the first differential signal leads, the second differential signal leads and the ground lead has a surface mounting segment adapted for being soldered onto a surface pad of a circuit board. The pair of first differential signal leads is a pair of transmitting differential signal leads Tx+ and Tx? in architecture of universal serial bus 3.0 (USB 3.0), and the pair of second differential signal leads is a pair of receiving differential signal leads Rx+ and Rx? in architecture of USB 3.0.