Abstract: A voice control device and a corresponding voice control method are provided. The voice control device includes a sound receiver, a sound converter, a voice identifier, and a central processing unit (CPU). The sound receiver receives a first sound signal. The sound converter converts the first sound signal from analog signal to digital signal. The voice identifier identifies a first voice signal from the first sound signal, performs a first comparison on the first voice signal and a second voice signal, and generates a wake-up signal according to the first comparison. When receiving the wake-up signal, the CPU enters a working state from a sleeping state, performs a second comparison on the first voice signal and the second voice signal, and takes over the voice input from the sound receiver and the sound converter according to the second comparison.

Abstract: A computer integral device includes a detection unit for detecting whether an external electronic device is in a determined position, wherein the external electronic device has been turned on; and a computer host, coupled to the detection unit. When the external electronic device is detected to be in the determined position, a power enable signal is sent to the computer host so as to activate the computer host to execute a computer turn on process. After the computer turn on process is executed by the computer host, the external electronic device may display image data received via a wireless communication link established between the computer host and the external electronic device.

Abstract: A graphics card, a multi-screen display system and a synchronous display method are disclosed. The disclosed method includes the following steps. Firstly, first clock signals are provided in parallel in response to a first clock signal transferred from a motherboard. A second clock signal is generated according to one of the first clock signals that are provided in parallel, wherein the oscillation frequency of the first clock signals is larger than the oscillating frequency of the second clock signal. Then, a set of display clocks are generated based on the second clock signal. The set of display clocks control the display of a set of screens, for synchronous multi-screen display.

Abstract: Provided are methods and systems for reducing memory bandwidth usage in a common buffer, multiple FIFO computing environment. The multiple FIFO's are arranged in coordination with serial processing units, such as in a pipeline processing environment. The multiple FIFO's contain pointers to entry addresses in a common buffer. Each subsequent FIFO receives only pointers that correspond to data that has not been rejected by the corresponding processing unit. Rejected pointers are moved to a free list for reallocation to later data.

Abstract: A pad structure is suitable for a circuit carrier or an integrated circuit chip. The pad structure includes an inner pad, a conductive via and an outer pad. The conductive via connects the inner pad. The outer pad connects the conductive via and further connects a conductive ball or a conductive bump. The outer diameter of the outer pad is greater than the outer diameter of the inner pad.

Abstract: High speed serial link techniques are provided. A system applying the high speed serial link technique comprises a relay unit and an amplifier. The relay unit receives a first pair of differential signals provided by a high speed transmitter of a first device, and provides the amplifier with at least one signal that is generated based on the first pair of differential signals. The amplifier amplifies and converts the signal provided by the relay unit to a second pair of differential signals to be received by a high speed receiver of a second device.

Abstract: An electronic system is provided, in which a smart chip, a smart chip controller, a processor, a system memory, and an access management module is provided. The smart chip controller communicates with the smart chip. The processor performs a mutual authentication with the smart chip. The system memory is accessible to the smart chip and the processor. The access management module is coupled between the processor and the smart chip controller. The access management module prevents the processor accessing a certain range of the system memory according to a block command from the smart chip controller, in response of that the mutual authentication between the processor and the smart chip is failed.

Abstract: A system and method for loading and playing multimedia information are disclosed. A navigator sends a series of play orders that each play order demands for playing a corresponding multimedia segment. A playing engine demands a loader to provide the corresponding multimedia segment according to related play order. A decoder is used to decode the provided multimedia segment for playback. Each play order may be delivered even the multimedia segment corresponding to its previous play order has not been played completely yet. The information discontinuity disadvantage can be eliminated since there is a smooth multimedia information stream provided for the decoder.

Abstract: The present invention provides an image/graphics data display mechanism for continuously displaying image/graphics data on multiple display devices of a computer that contains a system memory directly accessed by the computer's CPU during the CPU's power saving non-responding period, wherein there is provided sufficient system bandwidth, the mechanism of the present invention is independent on the resolution running on each display device and the number of display devices connected to the computer system. The mechanism provides two approaches to achieve continuous display of image/graphics data on multiple display devices computer system. In the first approach, a common clock source is used to coordinate display device horizontal synchronization signals, vertical synchronization signals, horizontal blank periods, and vertical blank periods. In the second approach, the mechanism has a control on the lengths and occurrences of the display device blank periods.

Abstract: An embodiment of the invention provides a data encryption method for an electrical device. The method comprises: generating an identification code corresponding to the electrical device; generating a temporary key according to the identification code; encrypting first data to generate a first secret key according to the temporary key and a first encryption mechanism; and encrypting the first secret key by a second encryption mechanism to generate an encrypted key.

Abstract: A method and apparatus for rendering overlapped objects are provided. In the method, multiple objects are sorted according to rendering properties thereof and placed into a source chain. As for a target object in the source chain, an object first overlapped with the target object is successively searched. If no overlapped object is found, the target object is moved to a target chain. Otherwise, a blending object is generated by blending an overlapping area of the target object and overlapped object according to an alpha-blending property thereof and the blending object and all non-overlapping areas of the target object and overlapped object are inserted respectively as a new object into the source chain. The above steps are repeated until all objects in the source chain are moved to the target chain. Finally, the objects in the target chain are rendered on an electronic device.

Abstract: A pre-culling method for the hidden surface removal of image objects is disclosed. The steps of the pre-culling method includes: transforming an eye coordinate from an eye space to a model space of a polygon when performing a rendering operation; and comparing a normal vector of the eye coordinate in the model space with the normal vector of each face of the polygon to determine whether each face of the polygon with respect to the eye coordinate is a front face or a back face.

Abstract: An input buffer is provided. The input buffer receives an input signal through an input terminal and outputs an output signal at an output terminal. The input circuit includes an input circuit and a level shifting circuit. The input circuit receives the input signal and generates a buffer signal according to the input signal. The level shifting circuit receives a first supply voltage and the buffer signal and generates the output signal at the output terminal according to the buffer signal and the first supply voltage. The first high level of the input signal is higher than a voltage level of the first supply voltage. When the input signal is at a first high level, the input circuit generates the buffer signal whose voltage level is between the first high level of the input signal and the voltage level of the first supply voltage.

Abstract: A microprocessor includes a cache memory and a data prefetcher. The data prefetcher detects a pattern of memory accesses within a first memory block and prefetch into the cache memory cache lines from the first memory block based on the pattern. The data prefetcher also observes a new memory access request to a second memory block. The data prefetcher also determines that the first memory block is virtually adjacent to the second memory block and that the pattern, when continued from the first memory block to the second memory block, predicts an access to a cache line implicated by the new request within the second memory block. The data prefetcher also responsively prefetches into the cache memory cache lines from the second memory block based on the pattern.

Abstract: A microprocessor includes a storage element having a plurality of locations each storing decryption key data associated with an encrypted program. A control register field (may be x86 EFLAGS register reserved field) specifies a storage element location associated with a currently executing encrypted program. The microprocessor restores from memory to the control register a previously saved value of the field in response to executing a return from interrupt instruction. A fetch unit fetches encrypted instructions of the currently executing encrypted program and decrypts them using the decryption key data stored the storage element location specified by the restored field value. A kill bit associated with each storage element location may be employed if the location is clobbered because more encrypted programs are multitasked than available locations in the storage element, in which case an exception is generated to re-load the clobbered decryption key data in response to the return from interrupt instruction.

Abstract: An embodiment of the invention provides a secure boot method for an electronic device including an embedded controller and a processor. The method includes the steps of verifying a secure loader by the embedded controller, unlocking a peripheral hardware of the electronic device by the embedded controller, and executing the secure loader by the processor.

Abstract: A data storage system and method are disclosed. The data storage system includes a first and a second memory and a memory control unit. The first memory is non-volatile, and the second memory is designed to store dynamic information of the first memory. The memory control unit includes a snapshot module, a recording module and a power-off recovery module, and is operative to handle the data loss of the second memory when an unexpected power-off occurs. When the power of the system is recovered, an initial address stored in the first memory by the snapshot module and link information and updating information recorded in the first memory by the recording module are obtained by the power-off recovery module to recovery the second memory.

Abstract: The present invention relates to a debugging apparatus for a computer system and a method thereof. A detecting unit detects if a debugging unit connects to the computer system. When a debugging unit connects to the computer system, the detecting unit produces a detecting signal, which contains information of a bus in the computer system electrically connected with the debugging unit. Then a selection unit selects the bus electrically connected with the debugging unit according to the detecting signal. Besides, a testing unit tests the computer system and produces a power-on self-test (POST) code, so that the selected bus can be used for outputting the POST code to the debugging unit. Thereby, the present invention can choose to use the bus reserved in the computer system for outputting the POST code to the debugging unit, and hence facilitating inspection personnel to debug the computer system.

Abstract: A data link transmitter in a PCI Express device for managing PCI-Express TLPs and DLLPs. The data link transmitter includes a priority system in which a DLLP for initializing flow control has highest priority, and an idle data character has lowest priority. Various embodiments include: a DLLP for power state entrance is lower priority than the DLLP for initializing flow control; a replay TLP for retry buffer re-transmission is lower priority than the DLLP for power state entrance, and a new TLP is lower priority than the replay TLP; an Ack/Nak DLLP is lower priority than the new TLP, a DLLP for updating flow control is lower priority than the Ack/Nak TLP, and a DLLP for acknowledging the DLLP for power state entrance is lower priority than the DLLP for updating flow control; a DLLP for updating flow control is lower priority than the DLLP for power state entrance.

Abstract: A control method for a memory is provided. The memory includes a plurality of storage units, each storing a plurality of bits. In a read mode, a read command is provided to the memory. The value of a most significant bit (MSB) of each storage unit is obtained and recorded. The value of the most significant bits is output. The value of a neighboring bit of each storage unit is obtained and recorded. The neighboring bit neighbors the most significant bit. The value of the neighboring bits is output.