Abstract: A storage control system includes a prefetch controller that identifies memory regions for prefetching according to temporal memory access patterns. The memory access patterns identify a number of sequential memory accesses within different time ranges and a highest number of memory accesses to the different memory regions within a predetermine time period.

Abstract: A storage processor is configured to identify a first disk drive and a second shadow drive associated with the first disk drive to an initiator. The storage processor receives storage commands from an initiator. When the storage commands access the first disk drive, the storage processor issues a first storage operation to the first disk drive. When the storage commands access the second shadow drive, the storage processor issues different storage operations to the first disk drive that are not supported by the initiator.

Abstract: An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths are arranged and operated so as to control the power consumption and data skew properties of the system. A configurable switching element may be used to form the interconnections at nodes, where a control signal and other information is used to manage the power status of other aspects of the configurable switching element. Time delay skew of data being transmitted between nodes of the network may be altered by exchanging the logical and physical line assignments of the data at one or more nodes of the network. A method of laying out an interconnecting motherboard is disclosed which reduces the complexity of the trace routing.

Abstract: A proxy manages write operations between devices that initiate write operations and one or more storage devices that store data for the write operations. A write log buffers the data for the write operations while the proxy waits for acknowledgments back from the storage device. The proxy is configured to copy at least some of the data from the write log into an overflow log when the data from the write operations is about to overflow the write log. The proxy device is further configured to maintain data consistency by delaying or blocking read operations until associated data from previously received write operations is acknowledged by the storage device.

Abstract: A flash memory management method and apparatus provides for the separation of the command and data paths so that communication paths may be used more efficiently, taking account of the characteristics of NAND FLASH circuits where the times to read, write and erase data differ substantially. A unique sequence identifier is assigned to a write command and associated data and association of the data and commands are validated prior to writing to the memory by comparing the unique sequence numbers of the data and command prior to executing the command. This comparison is performed after the data and command have traversed the communication paths.

Abstract: A heat dissipation device for an electronic device includes a base, a plurality of fins and at least one heat pipe. The base has a front surface and a rear surface opposite to the front surface. A heat-generating component of the electronic device is disposed adjacent to the rear surface. The plurality of fins extend from the front surface of the base. The heat pipe is disposed on the front surface of the base and in a cutout portion of the plurality of fins. The heat dissipation device, which removes heat from the heat-generating component, has a low profile and improved heat dissipation capability.

Abstract: A storage access system stores block data into physical address blocks in a storage media. A last one of the physical address blocks that is either unfilled or only partially filled with the block data is used for storing extra data associated with the data blocks. A first portion of the last one of the physical storage blocks may be reserved for overflow data for different sizes of the block data. A second portion of the last one of the physical storage blocks may be used to store the validation information for the block data.

Abstract: A storage system creates an abstraction of flash Solid State Device (SSD) media allowing random write operations of arbitrary size by a user while performing large sequential write operations of a uniform size to an SSD array. This reduces the number of random write operations performed in the SSD array and as a result increases performance of the SSD array. A control element determines when blocks from different buffers should be combined together or discarded based on fragmentation and read activity. This optimization scheme increases memory capacity and improves memory utilization and performance.

Abstract: A reliable and scalable system and method of broadcasting information to other computer nodes in a communication network requires only O(2) time steps. According to one aspect, after broadcasting data in O(1) steps to all nodes in the network, the system and method provides a distributed reliability protocol to ensure data delivery which only requires an additional O(1) steps. Therefore, unlike in prior art approaches where the root or co-root is responsible for the reliable data delivery, each node in the network takes on responsibility to deliver the message to a partner/neighborhood node. The broadcasting method and system of the can be used as building block for most collective/distributive operations, and provides a significant performance advantage in parallel computer systems that have multicast/broadcast capabilities.

Abstract: A storage processor is configured to identify a first disk drive and a second shadow drive associated with the first disk drive to an initiator. The storage processor receives storage commands from an initiator. When the storage commands access the first disk drive, the storage processor issues a first storage operation to the first disk drive. When the storage commands access the second shadow drive, the storage processor issues different storage operations to the first disk drive that are not supported by the initiator.

Abstract: An apparatus and method of managing the operation of a plurality of FLASH chips provides for a physical layer (PHY) interface to a FLASH memory circuit having a plurality of FLASH chips having a common interface bus. The apparatus has a PHY for controlling the voltages on the interface pins in accordance with a microprogrammable state machine. A data transfer in progress over the bus may be interrupted to perform another command to another chip on the shared bus and the data transfer may be resumed after completion of the another command.

Abstract: A system and method for managing the storage of data in non-volatile memory is described. In an aspect, the data may be described by metadata and a transaction log file that are checkpointed from a volatile memory into the non-volatile memory. Actions that take place between the last checkpointing of a metadata segment and log file segment are discovered by scanning the non-volatile memory blocks, taking account of a record of the highest sector in each block that is known to have been recorded. Any later transactions are discovered and used to update the recovered metadata so that the metadata correctly represents the stored data.

Abstract: A storage proxy includes a cache resource. A processor is configured to receive read and write requests sent from an initiator to a target over a first proxy path. The processor invalidates the cache lines when the read and write requests are redirected over a second direct path between the initiator and the target or when some other event indicates the data in the cache lines may no longer be consistent with corresponding data in the target. The processor identifies addresses for at least some of the cache lines that were previously valid and reloads the data for the identified addresses from the target back into some the cache lines when the read and write requests are redirected back over the first proxy path or when consistency can resumed between the data in the cache lines and corresponding data in the target.

Abstract: A storage access system provides consistent memory access times for storage media with inconsistent access latency and reduces bottlenecks caused by the variable time delays during memory write operations. Data is written iteratively into multiple different media devices to prevent write operations from blocking all other memory access operations. The multiple copies of the same data then allow subsequent read operations to avoid the media devices currently servicing the write operations. Write operations can be aggregated together to improve the overall write performance to a storage media. A performance index determines how many media devices store the same data. The number of possible concurrent reads varies according to the number of media devices storing the data. Therefore, the performance index provides different selectable Quality of Service (QoS) for data in the storage media.

Abstract: A proxy device monitors memory access operations between clients and a storage media. The proxy device stores at least some of the data from the storage media in a faster tiering media and provides the data from the faster tiering media to the clients for certain associated memory access operations. The proxy is also configured to monitor Small Computer System Interface (SCSI) communications between the clients and the storage media and invalidate at least some data in the tiering media when particular SCSI messages in the SCSI communications indicate the tiering media contains data that is out of sync with the data in the storage media.

Abstract: A storage proxy monitors storage access operations. Different address alignments are identified between the storage access operations and data blocks in a storage media. A dominant one of the address alignments is identified. Data blocks are mapped into the storage media to remove the dominant address alignment. An array of counters can be used to track the address alignments for different storage access sizes and the address alignment associated with the highest number of storage access operations is used as the dominant address alignment.

Abstract: A hardware search structure quickly determines the status of cache lines associated with a large disk array and at the same time reduces the amount of memory space needed for tracking the status. The search structure is configurable in hardware to different cache line sizes and different primary and secondary index sizes. A maintenance feature invalidates state record entries based both on their time stamps and on associated usage statistics.

Abstract: A multi-tiered cache manager and methods for managing multi-tiered cache are described. Multi-tiered cache manager causes cached data to be initially stored in the RAM elements and selects portions of the cached data stored in the RAM elements to be moved to the flash elements. Each flash element is organized as a plurality of write blocks having a block size and wherein a predefined maximum number of writes is permitted to each write block. The portions of the cached data may be selected based on a maximum write rate calculated from the maximum number of writes allowed for the flash device and a specified lifetime of the cache system.

Abstract: A data storage array is described, having a plurality of solid state disks configured as a RAID group. User data is mapped and managed on a page size scale by the controller, and the data is mapped on a block size scale by the solid state disk. The writing of data to the solid state disks of the RAID group is such that reading of data sufficient to reconstruct a RAID stripe is not inhibited by the erase operation of a disk to which data is being written.

Abstract: A memory system and a method for managing the system is described. The system is configured such a plurality of system controllers, which may be RAID controllers, receive requests from the external environment and distribute the requests to a plurality of memory modules such that data may be stored in the memory modules. A global sequence number is assigned to the data of a data stripe so that the operations related to the data stripe are performed in an ordered manner so that the data remains consistent. A plurality of system controllers may comprise a domain and access a plurality of memory controllers and a plurality of domains may include at least one common memory module.