Patents Assigned to Vishay General Semiconductor LLC
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Publication number: 20150091136Abstract: A semiconductor device such as a Zener diode includes a first semiconductor material of a first conductivity type and a second semiconductor material of a second conductivity type in contact with the first semiconductor material to form a junction therebetween. A first oxide layer is disposed over a portion of the second semiconductor material such that a remaining portion of the second semiconductor material is exposed. A polysilicon layer is disposed on the exposed portion of the second semiconductor material and a portion of the first oxide layer. A first conductive layer is disposed on the polysilicon layer. A second conductive layer is disposed on a surface of the first semiconductor material opposing a surface of the first semiconductor material in contact with the second semiconductor material.Type: ApplicationFiled: October 1, 2013Publication date: April 2, 2015Applicant: Vishay General Semiconductor LLCInventors: Shih-Kuan Chen, Wan-Lan Chiang, Ming-Tai Chiang, Chih-Ping Peng, Yih-Yin Lin
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Patent number: 8981381Abstract: A semiconductor device includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. The first portion of the first electrode has a lower Schottky potential barrier than the second portion of the first electrode. A second electrode is in contact with the first active layer. The second electrode establishes an ohmic junction with the first active layer.Type: GrantFiled: November 16, 2012Date of Patent: March 17, 2015Assignee: Vishay General Semiconductor LLCInventor: Yih-Yin Lin
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Patent number: 8982524Abstract: A low forward voltage drop transient voltage suppressor utilizes a low-reverse-voltage-rated PN diode electrically connected in parallel to a high-reverse-voltage-rated Schottky rectifier in a single integrated circuit device. The transient voltage suppressor is ideally suited to fix the problem of high forward voltage drop of PN diodes and high leakage of low reverse breakdown of Schottky rectifiers. The low-reverse-voltage PN rectifier can be fabricated through methods such as 1) double layers of epi (with higher concentration layer epi in the bottom) or 2) punch through design of PN diode by base with compression.Type: GrantFiled: February 6, 2012Date of Patent: March 17, 2015Assignee: Vishay General Semiconductor, LLCInventors: Lung-Ching Kao, Pu-Ju Kung, Yu-Ju Yu
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Patent number: 8981528Abstract: A semiconductor device such as a Schottky diode is provided which includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. A second electrode is in contact with the first active layer. The second electrode establishes an ohmic junction with the first active layer.Type: GrantFiled: November 16, 2012Date of Patent: March 17, 2015Assignee: Vishay General Semiconductor LLCInventor: Yih-Yin Lin
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Patent number: 8975719Abstract: A planar diode and method of making the same employing only one mask. The diode is formed by coating a substrate with an oxide, removing a central portion of the oxide to define a window through which dopants are diffused. The substrate is given a Ni/Au plating to provide ohmic contact surfaces, and the oxide on the periphery of the window is coated with a polyimide passivating agent overlying the P/N junction.Type: GrantFiled: August 2, 2013Date of Patent: March 10, 2015Assignee: Vishay General Semiconductor LLCInventors: Benson Wang, Kevin Lu, Warren Chiang, Max Chen
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Patent number: 8963296Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.Type: GrantFiled: January 31, 2014Date of Patent: February 24, 2015Assignee: Vishay General Semiconductor, LLCInventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
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Patent number: 8928065Abstract: A termination structure for a power transistor includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region to within a certain distance of an edge of the semiconductor substrate. A doped region has a second type of conductivity disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward a remote sidewall of the termination trench. A termination structure oxide layer is formed on the termination trench and covers a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate.Type: GrantFiled: October 21, 2010Date of Patent: January 6, 2015Assignee: Vishay General Semiconductor LLCInventors: Chih-Wei Hsu, Florin Udrea, Yih-Yin Lin
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Patent number: 8865526Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region.Type: GrantFiled: April 10, 2013Date of Patent: October 21, 2014Assignee: Vishay General Semiconductor LLCInventors: Ta-Te Chou, Yong-Qi Tian, Xian Li
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Patent number: 8853770Abstract: A termination structure is provided for a power transistor. The termination structure includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region toward an edge of the semiconductor substrate. A doped region having a second type of conductivity is disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward the edge of the semiconductor substrate. A termination structure oxide layer is formed on the termination trench covering a portion of the MOS gate and extends toward the edge of the substrate.Type: GrantFiled: March 16, 2010Date of Patent: October 7, 2014Assignee: Vishay General Semiconductor LLCInventors: Chih-Wei Hsu, Florin Udrea, Yih-Yin Lin
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Patent number: 8816468Abstract: A semiconductor rectifier includes a semiconductor substrate having a first type of conductivity. A first layer, which is formed on the substrate, has the first type of conductivity and is more lightly doped than the substrate. A second layer having a second type of conductivity is formed on the substrate and a metal layer is disposed over the second layer. The second layer is lightly doped so that a Schottky contact is formed between the metal layer and the second layer. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.Type: GrantFiled: August 31, 2011Date of Patent: August 26, 2014Assignee: Vishay General Semiconductor LLCInventors: Chih-Wei Hsu, Florin Udrea, Yih-Yin Lin
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Publication number: 20140217561Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.Type: ApplicationFiled: January 31, 2014Publication date: August 7, 2014Applicant: VISHAY GENERAL SEMICONDUCTOR, LLCInventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
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Patent number: 8796840Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.Type: GrantFiled: March 16, 2012Date of Patent: August 5, 2014Assignee: Vishay General Semiconductor LLCInventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
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Publication number: 20140199861Abstract: An electrical module includes a housing, at least one electrical component mounted within the housing and an electrical press-fit contact. The electrical press-fit contact is located in part within the housing and has a press fit portion and a stop portion at its distal end and a mounting portion at its proximal end. The mounting portion is electrically coupled to the electrical component. The press-fit portion is located exterior of the housing such that the stop portion is able to block movement of the press-fit section into the housing when a press-in force is introduced onto the press-in contact to press the press-fit contact into the housing.Type: ApplicationFiled: January 14, 2014Publication date: July 17, 2014Applicant: Vishay General Semiconductor LLCInventor: Emilio Mattiuzzo
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Publication number: 20140138697Abstract: A semiconductor device such as a Schottky diode is provided which includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. A second electrode is in contact with the first active layer. The second electrode establishes an ohmic junction with the first active layer.Type: ApplicationFiled: November 16, 2012Publication date: May 22, 2014Applicant: Vishay General Semiconductor LLCInventor: Yih-Yin Lin
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Publication number: 20140138698Abstract: A semiconductor device includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. The first portion of the first electrode has a lower Schottky potential barrier than the second portion of the first electrode. A second electrode is in contact with the first active layer.Type: ApplicationFiled: November 16, 2012Publication date: May 22, 2014Applicant: Vishay General Semiconductor LLCInventor: Yih-Yin Lin
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Publication number: 20140138764Abstract: A semiconductor device includes a semiconductor substrate having a first type of conductivity. A first layer is formed on the substrate having the first type of conductivity and is more lightly doped than the substrate. At least one trench is formed in the first layer. A dielectric layer lines the bottom surface and the sidewalls of the trench. A conducting material fills the trench. A lightly doped region is formed in the first layer having the second conductivity type. The lightly doped region is disposed below the bottom surface of the trench. A metal layer is disposed over the first layer and the conducting material. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.Type: ApplicationFiled: November 16, 2012Publication date: May 22, 2014Applicant: Vishay General Semiconductor LLCInventors: Chih Wei Hsu, Max Chen
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Publication number: 20140131842Abstract: An axially-mountable device includes a semiconductor chip comprising lower and upper electrical contacts. A lower die pad is electrically and mechanically connected to the lower electrical contact of the chip. An upper die pad is electrically and mechanically connected to the upper electrical contact of the chip. A first axially extending electrical lead is electrically and mechanically connected to the upper die pad and extends in a first axial direction. A second axially extending electrical lead is electrically and mechanically connected to the lower die pad and extends in a second axial direction that is opposite to the first axial direction. Packaging material encapsulates the semiconductor chip, the upper and lower die pads and a portion of the first and second axially extending leads. The first and second leads extend from the packaging material and are adapted to allow the device to be axially-mounted with another electrical component.Type: ApplicationFiled: November 10, 2012Publication date: May 15, 2014Applicant: Vishay General Semiconductor LLCInventors: Wan-Lan Chiang, Chih-Ping Peng, Hui-Ying Ding
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Patent number: 8643152Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.Type: GrantFiled: February 27, 2012Date of Patent: February 4, 2014Assignee: Vishay General Semiconductor, LLCInventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
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Publication number: 20130313684Abstract: A planar diode and method of making the same employing only one mask. The diode is formed by coating a substrate with an oxide, removing a central portion of the oxide to define a window through which dopants are diffused. The substrate is given a Ni/Au plating to provide ohmic contact surfaces, and the oxide on the periphery of the window is coated with a polyimide passivating agent overlying the P/N junction.Type: ApplicationFiled: August 2, 2013Publication date: November 28, 2013Applicant: VISHAY GENERAL SEMICONDUCTOR LLCInventors: Benson Wang, Kevin Lu, Warren Chiang, Max Chen
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Patent number: 8525222Abstract: A planar diode and method of making the same employing only one mask. The diode is formed by coating a substrate with an oxide, removing a central portion of the oxide to define a window through which dopants are diffused. The substrate is given a Ni/Au plating to provide ohmic contact surfaces, and the oxide on the periphery of the window is coated with a polyimide passivating agent overlying the P/N junction.Type: GrantFiled: March 25, 2005Date of Patent: September 3, 2013Assignee: Vishay General Semiconductor LLCInventors: Benson Wang, Kevin Lu, Warren Chiang, Max Chen