Patents Assigned to Vishay General Semiconductor LLC
  • Publication number: 20150091136
    Abstract: A semiconductor device such as a Zener diode includes a first semiconductor material of a first conductivity type and a second semiconductor material of a second conductivity type in contact with the first semiconductor material to form a junction therebetween. A first oxide layer is disposed over a portion of the second semiconductor material such that a remaining portion of the second semiconductor material is exposed. A polysilicon layer is disposed on the exposed portion of the second semiconductor material and a portion of the first oxide layer. A first conductive layer is disposed on the polysilicon layer. A second conductive layer is disposed on a surface of the first semiconductor material opposing a surface of the first semiconductor material in contact with the second semiconductor material.
    Type: Application
    Filed: October 1, 2013
    Publication date: April 2, 2015
    Applicant: Vishay General Semiconductor LLC
    Inventors: Shih-Kuan Chen, Wan-Lan Chiang, Ming-Tai Chiang, Chih-Ping Peng, Yih-Yin Lin
  • Patent number: 8981381
    Abstract: A semiconductor device includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. The first portion of the first electrode has a lower Schottky potential barrier than the second portion of the first electrode. A second electrode is in contact with the first active layer. The second electrode establishes an ohmic junction with the first active layer.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: March 17, 2015
    Assignee: Vishay General Semiconductor LLC
    Inventor: Yih-Yin Lin
  • Patent number: 8982524
    Abstract: A low forward voltage drop transient voltage suppressor utilizes a low-reverse-voltage-rated PN diode electrically connected in parallel to a high-reverse-voltage-rated Schottky rectifier in a single integrated circuit device. The transient voltage suppressor is ideally suited to fix the problem of high forward voltage drop of PN diodes and high leakage of low reverse breakdown of Schottky rectifiers. The low-reverse-voltage PN rectifier can be fabricated through methods such as 1) double layers of epi (with higher concentration layer epi in the bottom) or 2) punch through design of PN diode by base with compression.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: March 17, 2015
    Assignee: Vishay General Semiconductor, LLC
    Inventors: Lung-Ching Kao, Pu-Ju Kung, Yu-Ju Yu
  • Patent number: 8981528
    Abstract: A semiconductor device such as a Schottky diode is provided which includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. A second electrode is in contact with the first active layer. The second electrode establishes an ohmic junction with the first active layer.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: March 17, 2015
    Assignee: Vishay General Semiconductor LLC
    Inventor: Yih-Yin Lin
  • Patent number: 8975719
    Abstract: A planar diode and method of making the same employing only one mask. The diode is formed by coating a substrate with an oxide, removing a central portion of the oxide to define a window through which dopants are diffused. The substrate is given a Ni/Au plating to provide ohmic contact surfaces, and the oxide on the periphery of the window is coated with a polyimide passivating agent overlying the P/N junction.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: March 10, 2015
    Assignee: Vishay General Semiconductor LLC
    Inventors: Benson Wang, Kevin Lu, Warren Chiang, Max Chen
  • Patent number: 8963296
    Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: February 24, 2015
    Assignee: Vishay General Semiconductor, LLC
    Inventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
  • Patent number: 8928065
    Abstract: A termination structure for a power transistor includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region to within a certain distance of an edge of the semiconductor substrate. A doped region has a second type of conductivity disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward a remote sidewall of the termination trench. A termination structure oxide layer is formed on the termination trench and covers a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: January 6, 2015
    Assignee: Vishay General Semiconductor LLC
    Inventors: Chih-Wei Hsu, Florin Udrea, Yih-Yin Lin
  • Patent number: 8865526
    Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: October 21, 2014
    Assignee: Vishay General Semiconductor LLC
    Inventors: Ta-Te Chou, Yong-Qi Tian, Xian Li
  • Patent number: 8853770
    Abstract: A termination structure is provided for a power transistor. The termination structure includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region toward an edge of the semiconductor substrate. A doped region having a second type of conductivity is disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward the edge of the semiconductor substrate. A termination structure oxide layer is formed on the termination trench covering a portion of the MOS gate and extends toward the edge of the substrate.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: October 7, 2014
    Assignee: Vishay General Semiconductor LLC
    Inventors: Chih-Wei Hsu, Florin Udrea, Yih-Yin Lin
  • Patent number: 8816468
    Abstract: A semiconductor rectifier includes a semiconductor substrate having a first type of conductivity. A first layer, which is formed on the substrate, has the first type of conductivity and is more lightly doped than the substrate. A second layer having a second type of conductivity is formed on the substrate and a metal layer is disposed over the second layer. The second layer is lightly doped so that a Schottky contact is formed between the metal layer and the second layer. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: August 26, 2014
    Assignee: Vishay General Semiconductor LLC
    Inventors: Chih-Wei Hsu, Florin Udrea, Yih-Yin Lin
  • Publication number: 20140217561
    Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.
    Type: Application
    Filed: January 31, 2014
    Publication date: August 7, 2014
    Applicant: VISHAY GENERAL SEMICONDUCTOR, LLC
    Inventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
  • Patent number: 8796840
    Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: August 5, 2014
    Assignee: Vishay General Semiconductor LLC
    Inventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
  • Publication number: 20140199861
    Abstract: An electrical module includes a housing, at least one electrical component mounted within the housing and an electrical press-fit contact. The electrical press-fit contact is located in part within the housing and has a press fit portion and a stop portion at its distal end and a mounting portion at its proximal end. The mounting portion is electrically coupled to the electrical component. The press-fit portion is located exterior of the housing such that the stop portion is able to block movement of the press-fit section into the housing when a press-in force is introduced onto the press-in contact to press the press-fit contact into the housing.
    Type: Application
    Filed: January 14, 2014
    Publication date: July 17, 2014
    Applicant: Vishay General Semiconductor LLC
    Inventor: Emilio Mattiuzzo
  • Publication number: 20140138697
    Abstract: A semiconductor device such as a Schottky diode is provided which includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. A second electrode is in contact with the first active layer. The second electrode establishes an ohmic junction with the first active layer.
    Type: Application
    Filed: November 16, 2012
    Publication date: May 22, 2014
    Applicant: Vishay General Semiconductor LLC
    Inventor: Yih-Yin Lin
  • Publication number: 20140138698
    Abstract: A semiconductor device includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. The first portion of the first electrode has a lower Schottky potential barrier than the second portion of the first electrode. A second electrode is in contact with the first active layer.
    Type: Application
    Filed: November 16, 2012
    Publication date: May 22, 2014
    Applicant: Vishay General Semiconductor LLC
    Inventor: Yih-Yin Lin
  • Publication number: 20140138764
    Abstract: A semiconductor device includes a semiconductor substrate having a first type of conductivity. A first layer is formed on the substrate having the first type of conductivity and is more lightly doped than the substrate. At least one trench is formed in the first layer. A dielectric layer lines the bottom surface and the sidewalls of the trench. A conducting material fills the trench. A lightly doped region is formed in the first layer having the second conductivity type. The lightly doped region is disposed below the bottom surface of the trench. A metal layer is disposed over the first layer and the conducting material. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.
    Type: Application
    Filed: November 16, 2012
    Publication date: May 22, 2014
    Applicant: Vishay General Semiconductor LLC
    Inventors: Chih Wei Hsu, Max Chen
  • Publication number: 20140131842
    Abstract: An axially-mountable device includes a semiconductor chip comprising lower and upper electrical contacts. A lower die pad is electrically and mechanically connected to the lower electrical contact of the chip. An upper die pad is electrically and mechanically connected to the upper electrical contact of the chip. A first axially extending electrical lead is electrically and mechanically connected to the upper die pad and extends in a first axial direction. A second axially extending electrical lead is electrically and mechanically connected to the lower die pad and extends in a second axial direction that is opposite to the first axial direction. Packaging material encapsulates the semiconductor chip, the upper and lower die pads and a portion of the first and second axially extending leads. The first and second leads extend from the packaging material and are adapted to allow the device to be axially-mounted with another electrical component.
    Type: Application
    Filed: November 10, 2012
    Publication date: May 15, 2014
    Applicant: Vishay General Semiconductor LLC
    Inventors: Wan-Lan Chiang, Chih-Ping Peng, Hui-Ying Ding
  • Patent number: 8643152
    Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: February 4, 2014
    Assignee: Vishay General Semiconductor, LLC
    Inventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
  • Publication number: 20130313684
    Abstract: A planar diode and method of making the same employing only one mask. The diode is formed by coating a substrate with an oxide, removing a central portion of the oxide to define a window through which dopants are diffused. The substrate is given a Ni/Au plating to provide ohmic contact surfaces, and the oxide on the periphery of the window is coated with a polyimide passivating agent overlying the P/N junction.
    Type: Application
    Filed: August 2, 2013
    Publication date: November 28, 2013
    Applicant: VISHAY GENERAL SEMICONDUCTOR LLC
    Inventors: Benson Wang, Kevin Lu, Warren Chiang, Max Chen
  • Patent number: 8525222
    Abstract: A planar diode and method of making the same employing only one mask. The diode is formed by coating a substrate with an oxide, removing a central portion of the oxide to define a window through which dopants are diffused. The substrate is given a Ni/Au plating to provide ohmic contact surfaces, and the oxide on the periphery of the window is coated with a polyimide passivating agent overlying the P/N junction.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: September 3, 2013
    Assignee: Vishay General Semiconductor LLC
    Inventors: Benson Wang, Kevin Lu, Warren Chiang, Max Chen