Patents Assigned to Vishay General Semiconductor LLC
  • Publication number: 20080153243
    Abstract: Blanket implant diode which can be used for transient voltage suppression having a P+ substrate implanted with an N-type dopant blanket implant near a top surface of the substrate, creating a P? region. An oxide mask is layered adjacent to and above the P? region. The oxide mask is partially etched away from a portion of the P? region, creating an etched region. An N-type main function implant is implanted into the etched region, creating an N+ region above the P+ substrate and adjacent the P? region. And, a metal is layered above the oxide mask in the etched region to form an electrode. Terminations may be attached electrically to both sides of the P-N junction. Methods of making and using the present invention and methods for transient voltage suppression are also provided.
    Type: Application
    Filed: February 20, 2008
    Publication date: June 26, 2008
    Applicant: VISHAY GENERAL SEMICONDUCTORS, LLC
    Inventors: SHENG-HUEI DAI, YA-CHIN KING, CHUN-JEN HUANG, L.C. KAO
  • Publication number: 20080142880
    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region.
    Type: Application
    Filed: December 4, 2007
    Publication date: June 19, 2008
    Applicant: Vishay General Semiconductor LLC
    Inventors: Richard A. Blanchard, Jean-Michel Guillot
  • Publication number: 20080036057
    Abstract: A semiconductor device mountable to a substrate includes a semiconductor die and an electrically conductive lead frame having first and second end portions and a first attachment surface and a second attachment surface. The die electrically contacts the first end portion of the lead frame on the first attachment surface. An externally exposed housing encloses the semiconductor die and the first end portion of the lead frame, said housing including a metallic plate facing the second attachment surface of the lead frame.
    Type: Application
    Filed: August 9, 2007
    Publication date: February 14, 2008
    Applicant: Vishay General Semiconductor LLC
    Inventors: Ta-Te Chou, Xiong-Jie Zhang, Xian Li, Hai Fu, Yong-Qi Tian
  • Publication number: 20080013240
    Abstract: A low forward voltage drop transient voltage suppressor utilizes a low-reverse-voltage-rated PN diode electrically connected in parallel to a high-reverse-voltage-rated Schottky rectifier in a single integrated circuit device. The transient voltage suppressor is ideally suited to fix the problem of high forward voltage drop of PN diodes and high leakage of low reverse breakdown of Schottky rectifiers. The low-reverse-voltage PN rectifier can be fabricated through methods such as 1) double layers of epi (with higher concentration layer epi in the bottom) or 2) punch through design of PN diode by base with compression.
    Type: Application
    Filed: June 20, 2007
    Publication date: January 17, 2008
    Applicant: VISHAY GENERAL SEMICONDUCTOR, LLC
    Inventors: Lung-Ching Kao, Pu-Ju Kung, Yu-Ju Yu
  • Publication number: 20070090360
    Abstract: Blanket implant diode which can be used for transient voltage suppression having a P+ substrate implanted with an N-type dopant blanket implant near a top surface of the substrate, creating a P? region. An oxide mask is layered adjacent to and above the P? region. The oxide mask is partially etched away from a portion of the P? region, creating an etched region. An N-type main function implant is implanted into the etched region, creating an N+ region above the P+ substrate and adjacent the P? region. And, a metal is layered above the oxide mask in the etched region to form an electrode. Terminations may be attached electrically to both sides of the P-N junction. Methods of making and using the present invention and methods for transient voltage suppression are also provided.
    Type: Application
    Filed: May 2, 2006
    Publication date: April 26, 2007
    Applicant: Vishay General SemiConductors, LLC
    Inventors: Sheng-Huei Dai, Ya-Chin King, Chun-Jen Huang, L.C. Kao