Patents Assigned to Vishay General Semiconductor LLC
  • Publication number: 20130224911
    Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region.
    Type: Application
    Filed: April 10, 2013
    Publication date: August 29, 2013
    Applicant: Vishay General Semiconductor LLC
    Inventor: Vishay General Semiconductor LLC
  • Publication number: 20130168765
    Abstract: A termination structure is provided for a semiconductor device. The termination structure includes a semiconductor substrate having an active region and a termination region. A termination trench is located in the termination region and extends from a boundary of the active region toward an edge of the semiconductor substrate. A MOS gate is formed on a sidewall of the termination trench adjacent the boundary. At least one guard ring trench is formed in the termination region on a side of the termination trench remote from the active region. A termination structure oxide layer is formed on the termination trench and the guard ring trench. A first conductive layer is formed on a backside surface of the semiconductor substrate. A second conductive layer is formed atop the active region and the termination region.
    Type: Application
    Filed: January 4, 2012
    Publication date: July 4, 2013
    Applicant: Vishay General Semiconductor LLC
    Inventors: Yih-Yin Lin, Pai-Li Lin, Chih-Wei Hsu
  • Patent number: 8461646
    Abstract: A semiconductor rectifier is provided which includes a semiconductor substrate having a first type of conductivity. An epitaxial layer is formed on the substrate. The epitaxial layer has the first type of conductivity and is more lightly doped than the substrate. A plurality of floating gates is formed in the epitaxial layer and a metal layer is disposed over the epitaxial layer to form a Schottky contact therebetween. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: June 11, 2013
    Assignee: Vishay General Semiconductor LLC
    Inventor: Lung-Ching Kao
  • Patent number: 8426253
    Abstract: An integrated circuit device includes a die, a lead, and an electrically-conductive structure that is arranged to facilitate electrical communication between the die and the lead. The device also includes a potting material, in which the electrically conductive structure, the die, and at least part of the lead are embedded. An electrically-conductive housing encases the potting material and forms exterior packaging of the device. During manufacturing, the electrically-conductive structure, the die, and at least part of the lead may be arranged within the electrically-conductive housing either before or after the potting material is disposed in the housing. When the integrated circuit device is operating, heat is removable from the die via a thermal conduction path formed by the electrically-conductive structure, the potting material, and the electrically-conductive housing.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: April 23, 2013
    Assignee: Vishay General Semiconductor LLC
    Inventors: Peter Chou, Lucy Tian, Ivan Fu, Samuel Li, May-Luen Chou
  • Patent number: 8421214
    Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: April 16, 2013
    Assignee: Vishay General Semiconductor LLC
    Inventors: Ta-Te Chou, Yong-Qi Tian, Xian Li
  • Publication number: 20120252167
    Abstract: An integrated circuit device includes a die, a lead, and an electrically-conductive structure that is arranged to facilitate electrical communication between the die and the lead. The device also includes a potting material, in which the electrically conductive structure, the die, and at least part of the lead are embedded. An electrically-conductive housing encases the potting material and forms exterior packaging of the device. During manufacturing, the electrically-conductive structure, the die, and at least part of the lead may be arranged within the electrically-conductive housing either before or after the potting material is disposed in the housing. When the integrated circuit device is operating, heat is removable from the die via a thermal conduction path formed by the electrically-conductive structure, the potting material, and the electrically-conductive housing.
    Type: Application
    Filed: June 11, 2012
    Publication date: October 4, 2012
    Applicant: VISHAY GENERAL SEMICONDUCTOR LLC
    Inventors: Peter Chou, Lucy Tian, Ivan Fu, Samuel Li, May-Luen Chou
  • Patent number: 8269338
    Abstract: A semiconductor device mountable to a substrate includes a semiconductor die and an electrically conductive lead frame having first and second end portions and a first attachment surface and a second attachment surface. The die electrically contacts the first end portion of the lead frame on the first attachment surface. An externally exposed housing encloses the semiconductor die and the first end portion of the lead frame, said housing including a metallic plate facing the second attachment surface of the lead frame.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: September 18, 2012
    Assignee: Vishay General Semiconductor LLC
    Inventors: Ta-Te Chou, Xiong-Jie Zhang, Xian Li, Hai Fu, Yong-Qi Tian
  • Publication number: 20120223421
    Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.
    Type: Application
    Filed: February 27, 2012
    Publication date: September 6, 2012
    Applicant: VISHAY GENERAL SEMICONDUCTOR, LLC
    Inventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
  • Patent number: 8252633
    Abstract: The semiconductor assembly includes a first subassembly having a heat sink. Solder material is disposed on the exposed portion of a first surface of heat sink. A power semiconductor die is located on the first surface of the heat sink and is thermally coupled thereto by the solder material. A packaging patterned polymer layer is disposed on a second surface of the heat sink opposing the first surface and defines an interior surface portion of the heat sink. A semiconductor package is provided in which the first subassembly, solder material and die are located such that the interior surface portion of the second surface of the heat sink is not enclosed by the semiconductor package.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: August 28, 2012
    Assignee: Vishay General Semiconductor LLC
    Inventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
  • Publication number: 20120199902
    Abstract: A semiconductor rectifier is provided which includes a semiconductor substrate having a first type of conductivity. An epitaxial layer is formed on the substrate. The epitaxial layer has the first type of conductivity and is more lightly doped than the substrate. A plurality of floating gates is formed in the epitaxial layer and a metal layer is disposed over the epitaxial layer to form a Schottky contact therebetween. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.
    Type: Application
    Filed: February 4, 2011
    Publication date: August 9, 2012
    Applicant: VISHAY GENERAL SEMICONDUCTOR LLC
    Inventor: Lung-Ching Kao
  • Publication number: 20120200975
    Abstract: A low forward voltage drop transient voltage suppressor utilizes a low-reverse-voltage-rated PN diode electrically connected in parallel to a high-reverse-voltage-rated Schottky rectifier in a single integrated circuit device. The transient voltage suppressor is ideally suited to fix the problem of high forward voltage drop of PN diodes and high leakage of low reverse breakdown of Schottky rectifiers. The low-reverse-voltage PN rectifier can be fabricated through methods such as 1) double layers of epi (with higher concentration layer epi in the bottom) or 2) punch through design of PN diode by base with compression.
    Type: Application
    Filed: February 6, 2012
    Publication date: August 9, 2012
    Applicant: Vishay General Semiconductor, LLC
    Inventors: Lung-Ching Kao, Pu-Ju Kung, Yu-Ju Yu
  • Publication number: 20120168932
    Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.
    Type: Application
    Filed: March 16, 2012
    Publication date: July 5, 2012
    Applicant: Vishay General Semiconductor LLC
    Inventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
  • Patent number: 8198709
    Abstract: An integrated circuit device includes a die, a lead, and an electrically-conductive structure that is arranged to facilitate electrical communication between the die and the lead. The device also includes a potting material, in which the electrically conductive structure, the die, and at least part of the lead are embedded. An electrically-conductive housing encases the potting material and forms exterior packaging of the device. During manufacturing, the electrically-conductive structure, the die, and at least part of the lead may be arranged within the electrically-conductive housing either before or after the potting material is disposed in the housing. When the integrated circuit device is operating, heat is removable from the die via a thermal conduction path formed by the electrically-conductive structure, the potting material, and the electrically-conductive housing.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: June 12, 2012
    Assignee: Vishay General Semiconductor LLC
    Inventors: Peter Chou, Lucy Tian, Ivan Fu, Samuel Li, May-Luen Chou
  • Publication number: 20120098082
    Abstract: A semiconductor rectifier includes a semiconductor substrate having a first type of conductivity. A first layer, which is formed on the substrate, has the first type of conductivity and is more lightly doped than the substrate. A second layer having a second type of conductivity is formed on the substrate and a metal layer is disposed over the second layer. The second layer is lightly doped so that a Schottky contact is formed between the metal layer and the second layer. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.
    Type: Application
    Filed: August 31, 2011
    Publication date: April 26, 2012
    Applicant: VISHAY GENERAL SEMICONDUCTOR LLC
    Inventors: Chih-Wei HSU, Florin UDREA, Yih-Yin LIN
  • Patent number: 8138597
    Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: March 20, 2012
    Assignee: Vishay General Semiconductor LLC
    Inventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
  • Patent number: 8125056
    Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: February 28, 2012
    Assignee: Vishay General Semiconductor, LLC
    Inventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
  • Patent number: 8111495
    Abstract: A low forward voltage drop transient voltage suppressor utilizes a low-reverse-voltage-rated PN diode electrically connected in parallel to a high-reverse-voltage-rated Schottky rectifier in a single integrated circuit device. The transient voltage suppressor is ideally suited to fix the problem of high forward voltage drop of PN diodes and high leakage of low reverse breakdown of Schottky rectifiers. The low-reverse-voltage PN rectifier can be fabricated through methods such as 1) double layers of epi (with higher concentration layer epi in the bottom) or 2) punch through design of PN diode by base with compression.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: February 7, 2012
    Assignee: Vishay General Semiconductor, LLC
    Inventors: Lung-Ching Kao, Pu-Ju Kung, Yu-Ju Yu
  • Patent number: 8049271
    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: November 1, 2011
    Assignee: Vishay General Semiconductor LLC
    Inventors: Richard A. Blanchard, Jean-Michel Guillot
  • Patent number: 8048714
    Abstract: A semiconductor device mountable to a substrate includes a semiconductor die and an electrically conductive attachment region having a first attachment surface and a second attachment surface. The first attachment surface is arranged for electrical communication with the semiconductor die. A housing at least in part encloses the semiconductor die and the interlayer material. The housing has a recess disposed through the second attachment surface of the electrically conductive attachment region. A dielectric, thermally conductive interlayer material is located in the recess and secured to the housing. A metallic plate is located in the recess and secured to the interlayer material.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: November 1, 2011
    Assignee: Vishay General Semiconductor LLC
    Inventors: Ta-Te Chou, Xiong-Jie Zhang, Xian Li, Hai Fu, Yong-Qi Tian
  • Patent number: D654881
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: February 28, 2012
    Assignee: Vishay General Semiconductor LLC
    Inventors: Ta-Te Chou, Xiong-Jie Zhang, Xian Li, Hai Fu, Yong-Qi Tian