Patents Assigned to Vishay-Siliconix
  • Patent number: 11482601
    Abstract: A vertical trench shield device can include a plurality of gate structures and a termination structure surrounding the plurality of gate structures. The plurality of gate structures can include a plurality of gate regions and a corresponding plurality of gate shield regions. The plurality of gate structures can be disposed between the plurality of source regions, and extending through the plurality of body regions to the drift region. The plurality of gate structures can be separated from each other by a first predetermined spacing in a core area. A first set of the plurality of gate structures can extend fully to the termination structure. The ends of a second set of the plurality of gate structures can be separated from the termination structure by a second predetermined spacing. The first and second spacings can be configured to balance charge in the core area and the termination area in a reverse bias condition.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: October 25, 2022
    Assignee: Vishay-Siliconix, LLC
    Inventors: Jun Hu, M. Ayman Shibib, Misbah Azam, Kyle Terrill
  • Patent number: 11295949
    Abstract: A method of fabricating semiconductor devices including epitaxially depositing a heavily doped substrate layer that is substantially free of crystalline defects on a lightly doped virtual substrate. The device regions of the semiconductor devices can be fabricated about the heavily doped substrate layer before the lightly doped virtual substrate is removed.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: April 5, 2022
    Assignee: Vishay Siliconix, LLC
    Inventors: M. Ayman Shibib, Kyle Terrill
  • Patent number: 11218144
    Abstract: Semiconductor device with multiple independent gates. A gate-controlled semiconductor device includes a first plurality of cells of the semiconductor device configured to be controlled by a primary gate, and a second plurality of cells of the semiconductor device configured to be controlled by an auxiliary gate. The primary gate is electrically isolated from the auxiliary gate, and sources and drains of the semiconductor device are electrically coupled in parallel. The first and second pluralities of cells may be substantially identical in structure.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: January 4, 2022
    Assignee: Vishay-Siliconix, LLC
    Inventors: Sanjay Havanur, M. Ayman Shibib
  • Patent number: 11217541
    Abstract: A transistor and method of manufacturing an electrically active chip seal ring surrounding the gate, gate insulator and source structure of the active core area of the transistor. The chip seal ring can be electrically coupled to the gate to seal the active core area from intrusions of contaminants, impurities, defects and or the like.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: January 4, 2022
    Assignee: Vishay-Siliconix, LLC
    Inventors: M. Ayman Shibib, Kyle Terrill
  • Patent number: 11189702
    Abstract: Split gate semiconductor with non-uniform trench oxide. A metal oxide semiconductor field effect transistor (MOSFET) comprises a plurality of parallel trenches. Each such trench comprises a first electrode coupled to a gate terminal of the MOSFET and a second electrode, physically and electrically isolated from the first electrode. The second electrode is beneath the first electrode in the trench. The second electrode includes at least two different widths at different depths below a primary surface of the MOSFET. The trenches may be formed in an epitaxial layer. The epitaxial layer may have a non-uniform doping profile with respect to depth below a primary surface of the MOSFET. The second electrode may be electrically coupled to a source terminal of the MOSFET.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: November 30, 2021
    Assignee: Vishay Siliconix, LLC
    Inventors: M. Ayman Shibib, Misbah Azam, Chanho Park, Kyle Terrill
  • Patent number: 11131693
    Abstract: Vertical sense devices in vertical trench MOSFET. In accordance with an embodiment of the present invention, an electronic circuit includes a vertical trench metal oxide semiconductor field effect transistor configured for switching currents of at least one amp and a current sensing field effect transistor configured to provide an indication of drain to source current of the MOSFET. A current sense ratio of the current sensing FET is at least 15 thousand and may be greater than 29 thousand.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: September 28, 2021
    Assignee: Vishay-Siliconix, LLC
    Inventors: M. Ayman Shibib, Wenjie Zhang
  • Patent number: 11114559
    Abstract: A semiconductor device includes a first group of trench-like structures and a second group of trench-like structures. Each trench-like structure in the first group includes a gate electrode contacted to gate metal and a source electrode contacted to source metal. Each of the trench-like structures in the second group is disabled. The second group of disabled trench-like structures is interleaved with the first group of trench-like structures.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: September 7, 2021
    Assignee: Vishay-Siliconix, LLC
    Inventors: Chanho Park, Kyle Terrill
  • Patent number: 11004841
    Abstract: Disclosed are semiconductor devices that include additional gate pads, and methods of fabricating and testing such devices. A device may include a first gate pad, a second gate pad, and a third gate pad. The first gate pad is connected to a gate including a gate oxide layer. The second and third gate pads are part of an electro-static discharge (ESD) protection network for the device. The ESD protection network is initially isolated from the first gate pad and hence from the gate and gate oxide layer. Accordingly, gate oxide integrity (GOI) testing can be effectively performed and the reliability and quality of the gate oxide layer can be checked. The second gate pad can be subsequently connected to the first gate pad to enable the ESD protection network, and the third gate pad can be subsequently connected to an external terminal when the device is packaged.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: May 11, 2021
    Assignee: VISHAY SILICONIX, LLC
    Inventors: Chanho Park, Ayman Shibib, Kyle Terrill
  • Patent number: 10950699
    Abstract: A vertical trench shield device can include a plurality of gate structures and a termination structure surrounding the plurality of gate structures. The plurality of gate structures can include a plurality of gate regions and a corresponding plurality of gate shield regions. The plurality of gate structures can be disposed between the plurality of source regions, and extending through the plurality of body regions to the drift region. The plurality of gate structures can be separated from each other by a first predetermined spacing in a core area. A first set of the plurality of gate structures can extend fully to the termination structure. The ends of a second set of the plurality of gate structures can be separated from the termination structure by a second predetermined spacing. The first and second spacings can be configured to balance charge in the core area and the termination area in a reverse bias condition.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: March 16, 2021
    Assignee: Vishay-Siliconix, LLC
    Inventors: Jun Hu, M. Ayman Shibib, Misbah Azam, Kyle Terrill
  • Patent number: 10930591
    Abstract: Trench MOSFET with self-aligned body contact with spacer. In accordance with an embodiment of the present invention, a plurality of gate trenches are formed into a semiconductor substrate. A body contact trench is formed into the semiconductor substrate in a mesa between the gate trenches. Spacers are deposited on sidewalls of the body contact trench. An ohmic body contact is implanted into the semiconductor substrate through the body contact trench utilizing the spacers to self-align the implant. A body contact trench extension may be etched into the semiconductor substrate through the body contact trench utilizing the spacers to self-align the etch, prior to the implant.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: February 23, 2021
    Assignee: Vishay-Siliconix, LLC
    Inventors: Lingpeng Guan, Kyle Terrill, Seokjin Jo
  • Patent number: 10903163
    Abstract: Trench MOSFET with self-aligned body contact with spacer. In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor substrate, and at least two gate trenches formed in the semiconductor substrate. Each of the trenches comprises a gate electrode. The semiconductor device also includes a body contact trench formed in the semiconductor substrate between the gate trenches. The body contact trench has a lower width at the bottom of the body contact trench and an ohmic body contact implant beneath the body contact trench. The horizontal extent of the ohmic body contact implant is not greater than the lower width of the body contact trench.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: January 26, 2021
    Assignee: Vishay-Siliconix, LLC
    Inventors: Lingpeng Guan, Kyle Terrill, Seokjin Jo
  • Patent number: 10833063
    Abstract: A multi-gate High Electron Mobility Transistor (HEMT) can include a Two-Dimension Electron Gas (2DEG) channel between the drain and the source. A first gate can be disposed proximate the 2DEG channel between the drain and source. The first gate can be configured to deplete majority carriers in the 2DEG channel proximate the first gate when a potential applied between the first gate and the source is less than a threshold voltage associated with the first gate. A second gate can be disposed proximate the 2DEC channel, between the drain and the first gate. The second gate can be electrically coupled to the drain. The second gate can be configured to deplete majority carriers in the 2DEG channel proximate the second gate when a potential applied between the second gate and the 2DEG channel between the second gate and the first gate is less than a threshold voltage associated with the second gate.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: November 10, 2020
    Assignee: Vishay Siliconix, LLC
    Inventors: Muhammad Ayman Shibib, Chungchi Gina Liao
  • Patent number: 10693288
    Abstract: A protection circuit can include a first clamping sub-circuit, a first switching sub-circuit and a first resistive sub-circuit coupled in series between a first and second node. The protection circuit can also include a second clamping sub-circuit, a second switching sub-circuit and a second resistive sub-circuit coupled in series between the second and first nodes. The first and second clamping sub-circuits and the first and second resistive sub-circuits can be configured to bias a switching shunt sub-circuit. The switching shunt sub-circuit can be configured to short the first and second nodes together in response to a bias potential from the first and second clamping sub-circuits and the first and second resistive sub-circuits indicative of an over-voltage, Electrostatic Discharge (ESD) or similar event. The first and second switching sub-circuits can be configured to prevent the occurrence of a current path through the first and second resistive sub-circuits at the same time.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: June 23, 2020
    Assignee: Vishay Siliconix, LLC
    Inventors: Muhammed Ayman Shibib, Chungchi Gina Liao
  • Patent number: 10665711
    Abstract: A high-electron-mobility transistor (HEMT) includes a substrate layer of silicon, a first contact disposed on a first surface of the substrate layer, and a number of layers disposed on a second surface of the substrate layer opposite the first surface. A second contact and a gate contact are disposed on those layers. A trench containing conducting material extends completely through the layers and into the substrate layer. In an embodiment of the HEMT, the first contact is a drain contact and the second contact is a source contact. In another embodiment of the HEMT, the first contact is a source contact and the second contact is a drain contact.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 26, 2020
    Assignee: VISHAY SILICONIX, LLC
    Inventors: Ayman Shibib, Kyle Terrill, Yongping Ding, Jinman Yang
  • Patent number: 10651303
    Abstract: A device includes a first high electronic mobility transistor (HEMT) and a second HEMT. The first HEMT includes a first gate, a source coupled to the first gate, and a drain coupled to the first gate. The second HEMT includes a second gate coupled to the source and to the drain. The second HEMT has a lower threshold voltage than the first HEMT.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: May 12, 2020
    Assignee: Vishay Siliconix, LLC
    Inventors: Ayman Shibib, Kyle Terrill
  • Patent number: 10630071
    Abstract: Presented systems and methods can facilitate efficient switching and protection in electronic systems. A system can comprise: an input operable to receive a signal; an adjustable component configurable to operate in a first mode which includes a low resistance and the component configurable to operate in a second mode which includes a current limiting operation in which the second mode enables continued operation in conditions that are unsafe for operation in the first mode; and an output operable to forward a signal. The adjustable component can be configurable to turn off if unsafe to operate in either the first mode or second mode. The first mode can include a relatively large component configuration with a relatively low drain to source on resistance. Utilizing a small component configuration in the second mode can include a relatively increased gate to source voltage compared to a large component configuration in the second mode.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: April 21, 2020
    Assignee: Vishay-Siliconix, LLC
    Inventors: Kyle Terrill, Trang Vu
  • Patent number: 10622994
    Abstract: A driver for a semiconductor switching device can be configured to step down a supply voltage to generate a first drive voltage. The driver can also generate a second drive voltage equal to the potential difference between the supply voltage and the first drive voltage. The driver can supply the first drive voltage to a control gate of the semiconductor switching device during a first state of a control signal, and a reverse polarity of the second drive voltage during a second state of the control signal.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: April 14, 2020
    Assignee: Vishay-Siliconix, LLC
    Inventor: Sanjay Havanur
  • Patent number: 10600902
    Abstract: A self repairing field effect transistor (FET) device, in accordance with one embodiment, includes a plurality of FET cells each having a fuse link. The fuse links are adapted to blow during a high current event in a corresponding cell.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: March 24, 2020
    Assignee: Vishay Siliconix, LLC
    Inventor: Robert Xu
  • Patent number: 10546840
    Abstract: In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: January 28, 2020
    Assignee: Vishay Siliconix, LLC
    Inventors: Kyle Terrill, Frank Kuo, Sen Mao
  • Patent number: 10546750
    Abstract: Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: January 28, 2020
    Assignee: Vishay-Siliconix
    Inventors: Hamilton Lu, The-Tu Chau, Kyle Terrill, Deva N. Pattanayak, Sharon Shi, Kuo-In Chen, Robert Xu