Abstract: A method for fabricating a diode is disclosed. In one embodiment, the method includes forming a Schottky contact on an epitaxial layer of silicon carbide (SiC) and annealing the Schottky contact at a temperature in the range of 300° C. to 700° C. The Schottky contact is formed of a layer of molybdenum.

Abstract: A method for fabricating a MOSFET having an active area and an edge termination area is disclosed. The method includes forming a first plurality of implants at the bottom of trenches located in the active area and in the edge termination area. A second plurality of implants is formed at the bottom of the trenches located in the active area. The second plurality of implants formed at the bottom of the trenches located in the active area causes the implants formed at the bottom of the trenches located in the active area to reach a predetermined concentration. In so doing, the breakdown voltage of both the active and edge termination areas can be made similar and thereby optimized while maintaining advantageous RDson.

Abstract: Methods of fabricating a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device are described. A column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant.

Abstract: An LDMOS (laterally diffused metal oxide semiconductor) structure connects the source to a substrate and also the gate shield while utilizing a reduced area for such contacts. The structure includes an electrically conductive substrate layer, a source, and a drain contact; the drain contact is separated from the substrate layer by at least one intervening layer. An electrically conductive trench-like feed-through element passes through the intervening layer and contacts the substrate and the source to electrically connect the drain contact and the substrate layer.

Abstract: High mobility P-channel power metal oxide semiconductor field effect transistors. In accordance with an embodiment of the present invention, a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, or equivalents, and the current flow is in the [110] direction, or equivalents, when a negative potential is applied to the gate with respect to the source. The enhanced channel mobility of holes leads to a reduction of the channel portion of the on-state resistance, thereby advantageously reducing total “on”resistance of the device.

Abstract: A method for producing a power MOSFET. The method includes fabricating a plurality of layers of a power MOSFET to produce an upper surface active area and performing a chemical mechanical polishing process on the active area to produce a substantially planar surface. A metalization deposition process is then performed on the substantially planar surface and the fabrication of the power MOSFET is subsequently completed.

Abstract: A method, in one embodiment, can include forming a plurality of trenches in a body region for a vertical metal-oxide semiconductor field-effect transistor (MOSFET). In addition, the method can include angle implanting source regions into the body region. Furthermore, dielectric material can be grown within the plurality of trenches. Gate polysilicon can be deposited within the plurality of trenches. Moreover, the method can include chemical mechanical polishing the gate polysilicon. The method can also include etching back the gate polysilicon within the plurality of trenches.

Abstract: In one embodiment, a Super Junction metal oxide semiconductor field effect transistor (MOSFET) device can include a substrate and a charge compensation region located above the substrate. The charge compensation region can include a plurality of columns of P type dopant within an N type dopant region. In addition, the Super Junction MOSFET can include a termination region located above the charge compensation region and the termination region can include an N? type dopant. Furthermore, the Super Junction MOSFET can include an edge termination structure. The termination region includes a portion of the edge termination structure.

Abstract: Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.

Abstract: High mobility P-channel power metal oxide semiconductor field effect transistors. In accordance with an embodiment of the present invention, a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, or equivalents, and the current flow is in the [110] direction, or equivalents, when a negative potential is applied to the gate with respect to the source. The enhanced channel mobility of holes leads to a reduction of the channel portion of the on-state resistance, thereby advantageously reducing total “on” resistance of the device.

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) transistor structure with improved unclamped inductive switching immunity. The LDMOS includes a substrate and an adjacent epitaxial layer both of a first conductivity type. A gate structure is above the epitaxial layer. A drain region and a source region, both of a second conductivity type, are within the epitaxial layer. A channel is formed between the source and drain region and arranged below the gate structure. A body structure of the first conductivity type is at least partially formed under the gate structure and extends laterally under the source region, wherein the epitaxial layer is less doped than the body structure. A conductive trench-like feed-through element passes through the epitaxial layer and contacts the substrate and the source region. The LDMOS includes a tub region of the first conductivity type formed under the source region, and adjacent laterally to and in contact with said body structure and said trench-like feed-through element.

Abstract: A boost converter circuit that includes a power supply, an inductor coupled to the power supply to receive current from the power supply, a diode coupled to receive current from the inductor and coupled to provide current to a load as an output, an inductor switch coupled to a node between the inductor and the diode for selectively switching current from the inductor anyway from the diode, and a ramp circuit. The ramp circuit is coupled to the node between the inductor and the diode, and is configured to selectively sample a voltage at the node between the inductor and the diode via a sampling switch and use the sampled signal to produce a stabilization ramp to stabilize the output.

Abstract: A split gate field effect transistor device. The device includes a split gate structure having a trench, a gate electrode and a source electrode. A first poly layer is disposed within the trench and is connected to the gate electrode. A second poly layer connected to the source electrode, wherein the first poly layer and the second poly layer are independent.

Abstract: In a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device, a column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant.

Abstract: A split gate semiconductor device includes a trench gate having a first electrode region and a second electrode region that are separated from each other by a gate oxide layer and an adjacent dielectric layer. The boundary of the gate oxide layer and the dielectric layer is curved to avoid a sharp corner where the gate oxide layer meets the sidewalls of the trench.

Abstract: A silicon carbide device has a termination region that includes a mesa region that links the termination region to an active area of the device and that includes one or more trenches.

Abstract: Systems and methods for narrow semiconductor trench structures. In a first method embodiment, a method for forming a narrow trench comprises forming a first layer of insulating material on a substrate and creating a trench through the first layer of insulating material and into the substrate. A second insulating material is formed on the first layer and on exposed portions of the trench and the second insulating material is removed from the first layer of insulating material and the bottom of the trench. The trench is filled with an epitaxial material and the first layer of insulating material is removed. A narrow trench is formed by the removal of remaining portions of the second insulating material.

Abstract: An SiC Schottky diode die or a Si Schottky diode die is mounted with its epitaxial anode surface connected to the best heat sink surface in the device package. This produces a substantial increase in the surge current capability of the device.

Abstract: Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.

Abstract: In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.