Abstract: An ESD protection device for protecting semiconductor devices from electrostatic discharge includes a metal pad of the semiconductor device, a first charge sink, and a first MOS transistor. The first MOS transistor is placed under the metal pad. The first MOS transistor is coupled as a switch between the first charge sink and the metal pad. In addition, the metal pad operates as a gate of the first MOS transistor. Upon static electricity of a high magnitude of voltage being placed on the metal pad, the first MOS transistor turns on and the static electricity is discharged to the first charge sink.

Abstract: A transistor is formed which has improved hot carrier immunity. On a substrate, between two source/drain regions, a gate region is formed over a dielectric region. An implant is used to dope the source/drain regions. After doping the source/drain regions, a tilted angle nitrogen implant is performed to implant nitrogen into areas of the dielectric region overlaying the drain/source regions of the transistor. The tilted angle nitrogen implant may be performed before or after forming spacer regions on sides of the gate region.

Abstract: A method an apparatus for generating and storing a connectivity data structure representing a circuit layout. The data structure includes a list of pointers representing cells of the layout, and each cell pointer points to an entry in a cell table. The cell table entries include a field pointing to a cell types table, and another entry pointing to a boundary table, which itself stores fields identifying edges and adjacent cells. The edge entries point to an edge table including fields representing the endpoints of the edge. The endpoint fields point to a point table including coordinates of the endpoint in question and a move field identifying whether the edge has been moved in a layout modification routine. The method of generating this data structure involves entering a layout, adding new cells one by one, and when each new cell is added, generating entries for all the cells, boundaries, edges and edge endpoints of the new cell, and storing them in the data structure.

Abstract: A ring-style, multi-stage VCO of a phase lock loop circuit includes two or more differential amplifier stages. The phase lock loop includes a lowpass filter connected between a control voltage terminal and a voltage-to-current converter stage, which includes a first source-follower MOS transistor M1 with a source resistor R1 and a second diode-connected MOS transistor M2 connected to its drain terminal. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN.sub.-- terminal. The drain terminal of MOS transistor M4 provides an OUT.sub.

Abstract: An input buffer for a CMOS integrated circuit comprises parallel pairs of complementary PMOS pull-up and NMOS pull-down transistors. Floating NMOS gates are capacitively coupled to V.sub.SS by a first-level metalization pattern. The metal-to-gate overlap capacitance and the gate-to-drain overlap capacitance define a voltage divider that leaves the gate at a small positive voltage during an electrostatic discharge event. This ensures that all NMOS transistors of a buffer enter a conducting bipolar mode before any of them enters second breakdown. This arrangement maximizes input-buffer protection from electrostatic discharge events. The novel NMOS arrangement is readily compatible with gate array designs.

Abstract: A coating system for detecting the presence of contaminants carried by a fluid that is applied as a coating on a workpiece. A tube guides the fluid along a flow path to the workpiece. A light source illuminates the fluid along at least a portion of the flow path, and this light is scattered by any contaminants present in the fluid. Light scattered by the contaminant particles is more intense than light scattered by the other fluid particles, and this brighter scattered light is detected by a light detector positioned adjacent to the fluid flow path. If one or more contaminant particles is detected in the fluid, a warning signal can be given and/or the flow of fluid can be stopped. This coating system is particularly well suited for use in a spin-on coating process that applies a liquid, such as a photoresist material or a dielectric material, to a semiconductor wafer or other workpiece that is secured to a rotating turntable.

Abstract: A method for selectively controlling the operation of a computer system so that the computer system is selectively caused to execute instructions of a first predetermined bit length or instructions of a second predetermined bit length. The method comprises the preliminary steps of storing instruction data in a set of EVEN instruction storage locations; storing instruction data in a set of ODD instruction locations; establishing an EVEN execution pointer; and establishing an ODD execution pointer. At a first given time, either the EVEN execution pointer is incremented by a predetermined COUNT or the ODD execution pointer is incremented by the predetermined COUNT; but both pointers are not simultaneously incremented by the COUNT. The method causes an instruction to be executed, which instruction was stored entirely in either an EVEN instruction location or entirely in an ODD instruction location.

Abstract: An improved fluid distribution head for a plasma processing system characterized by a non-planar dispersion plate provided with a plurality of apertures formed therethrough, and a mechanism for flowing a process gas through the apertures of the dispersion plate. The non-planar dispersion plate is preferably provided with a concave, spherical portion having a radius of curvature of at least four feet. The mechanism for flowing the process gas through the apertures includes an enclosure defining a chamber which communicates with the dispersion plate, a gas inlet communicating with the chamber, and a source of process gas coupled to the gas inlet. The fluid distribution head preferably forms a part of a complete plasma processing system including a wafer pedestal and an R.F. generator coupled to the pedestal to form a plasma between the dispersion plate and the wafer from the process gas flowing from the dispersion plate.

Abstract: A method of fabricating BiCMOS devices, and the resultant BiCMOS device, are disclosed. According to the present invention, over-etching to the substrate on the deposited polysilicon emitter is prevented by providing additional oxide beneath a polysilicon layer as an etch stop. Despite inclusion of an oxide to define an end-point during patterning of an emitter, fabrication complexity is reduced by avoiding additional SAT masking and oxidation steps.

Abstract: Semiconductor wafers are processed in a semiconductor diffusion furnace. During processing, the semiconductor wafers are placed in a quartz tube. Also during processing, a laser beam is transmitted below a top surface of the quartz tube. While the quartz tube is not sagging, the laser beam is detected with a detector. When the top surface of the quartz tube sags so that the laser beam is obstructed by the top surface, the laser beam is no longer detected by the detector. At this point the detector will alert an operator of the system that the top surface of the quartz tube is sagging so that the laser beam is obstructed by the top surface. The operator of the semiconductor diffusion furnace then may replace the quartz tube before damage is done to the semiconductor wafers.

Abstract: Method and apparatus for improving the cooling of a molded package assembly for one or more integrated-circuit dies, each of which is attached to a die-attach paddle portion of a lead frame. The improved package includes a molded-plastic package body which is formed around the lead frame and the attached integrated-circuit die. The package body has one or more through-holes formed through it for passage of air, where the air currents are drawn by convection or forced through the through-hole for cooling the integrated-circuit die attached the die-attach paddle. The die-attach paddle has a corresponding hole formed in it and the through-hole formed in the package body is located adjacent to the hole in the die-attach paddle to form a through-channel through the lead frame and the molded plastic body for convection cooling. The die-attach paddle is covered with molded plastic material so that the die-attach paddle is not exposed in the through-channel.

Abstract: An integrated circuit device including a substrate, a gate structure formed over the substrate, a channel formed in the substrate under the gate, a lightly-doped drain-side LDD region formed in the substrate adjacent to a drain-side of the channel (preferably by a LATID process), a drain region formed in the substrate near to the drain-side LDD region, and a drain-side DDD region substantially separating the drain-side LDD region from the drain region. Preferably, the integrated circuit device is symmetrically formed such that a lightly-doped source-side LDD region is formed in the substrate adjacent to a source-side of the channel (again preferably by a LATID process), a source region is formed in the substrate near to the source-side LDD region, and a source-side DDD region is formed in the substrate to substantially separate the source-side LDD region from the source region. Further preferably, the DDD regions substantially isolate the source and drain from a bulk portion of the substrate.

Abstract: A programmable output pad is disclosed that reduces ground bounce noise and power supply noise under different power supply values and under different load conditions. The programmable output pad comprises a pre-driver, a driver, and a controllable delay. The pre-driver transfers a signal from the input of the output pad to the driver which, in turn, transfers the signal from the pre-driver to an output of the output pad. The controllable delay provides one or more resistors, transistors, transmission gates, or equivalents thereof at the input of the driver which are controlled in order to provide a plurality of different time delays. By selecting these different time delays, the activation of the driver is delayed by different amounts of time. For a given power supply value and load condition, selection of the proper delay effectively reduces both the ground bounce noise on the ground supply of the programmable output pad and the noise on the power supply of the programmable output pad.

Abstract: An integrated circuit fabrication method begins with semiconductor devices formed on a substrate. A patterned metal layer is deposited on the substrate to connect the semiconductor devices. A nitride layer is deposited over the metal layer and substrate. The nitride layer topography comprises hills located over metal regions and valleys located over non-metal regions. Spin-on-glass (SOG) is deposited over the nitride layer, thereby filling the valleys and covering the hills. The SOG layer and the nitride layer hills are etched back at substantially the same etch rate, using plasma etching, to form a planar surface. An oxide layer is then deposited over the planar surface to encapsulate the semiconductor devices, metal layer, nitride layer and SOG layer. Vias may then be etched through the oxide layer and the nitride layer to expose portions of the underlying metal layer and facilitate upper layer metal connections thereto.

Abstract: An output buffer contains a totem-pole structure of four CMOS transistors. The top two are PMOS devices and the bottom two are NMOS devices. The top and bottom transistors function as output current switches which alternatively turn on and off the current flow from either VSS or VDD to the resistive termination load Rt. The middle two devices are connected to DC voltage references which control a precise amounts of current sourced to a load using a precision current source and sunk from a load using and to a precision current sink. The reference voltages for the precision current source and the current sink uses a negative feedback circuit which is referenced to a resistor ladder and a current source controlled by a band-gap reference source. This allows for on-chip referencing of ECL levels and control of reference voltages and currents in spite of variation is process, voltage, and temperature. Internal ECL reference levels signals V.sub.OL and V.sub.OH are used to control the output levels.

Abstract: A "charge-kicker" programming circuit for programming anti-fuse links in integrated-circuit memory devices permits smaller feature sizes and a correspondingly lower breakdown voltage by using reduced internal voltage levels to generate a gate voltage for a series pass transistor. A series pass transistor gates a high voltage programming signal (typically 13 volts) to a high-voltage programming line. Selection circuits steer the high voltage programming signal to various columns of anti-fuse elements. A fixed voltage, insufficient to turn on the series pass transistor is applied to the gate terminal of the series pass transistor. An alternating voltage is applied directly onto the gate terminal of the series pass transistor through a capacitor so that the peaks of the alternating voltage turn on the series pass transistor which gates the programming voltage to the main high voltage programming line for the anti-fuse memory array.

Abstract: A method of identifying a weakest interface where delamination is most likely to occur in a multi-layer dielectric film stack formed on a semiconductor wafer includes scribing processed layers including the multi-layer dielectric film stack with an applied force of a selected and constant magnitude, measuring the depth of a cavity formed in the processed layers by such scribing, and identifying the weakest interface by comparing the measured depth against the known depths of the interfaces between adjacent layers of the multi-layer dielectric film stack.

Abstract: An anti-fuse structure formed in accordance with the present invention includes a conductive layer base. A layer of anti-fuse material overlies the conductive base layer. On top of the anti-fuse layer is an insulating layer, in which a via hole is formed to the anti-fuse layer. The lateral dimension of the via hole is less than about 0.8 microns. Provided in the via hole is a conductive non-Al plug including a conductive barrier material such as TiN or TiW to contact the anti-fuse material and overlie the insulating layer. Tungsten is effectively used as the non-Al plug. An electrically conductive layer is formed over the plug and is separaged from the anti-fuse layer by at least one-half the depth of the via hole. The structure is then programmable by application of a programming voltage and readable by application of a sensing voltage, which is lower than the programming voltage.

Abstract: A single bit status register includes an input flip-flop, an asynchronous latch having an input coupled to an output of the input flip-flop, a comparator for comparing the outputs of the flip-flop and the latch, and an output stage which provides an error output when the comparator determines that the outputs of the flip-flop and the latch are not the same. In this fashion, it is known when a "read" of the status register is invalid due to the presence of the error output. Preferably, the register also includes a reset disabling mechanism which prevents the input flip-flop from being reset until a valid read has occurred. A n-bit status register includes n register sections, where each register section includes an input flip-flop, an asynchronous latch having an input coupled to an output of the input flip-flop, and a register section comparison mechanism for comparing the outputs of the flip-flop and the latch in that register section.

Abstract: The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.