Abstract: A method determines approximate propagation delay through logic devices within a library. Each logic cell within the library is characterized at baseline conditions to obtain parameters for each logic cell which define propagation delay through each logic cell at the baseline conditions. A subset of the logic cells are characterized at conditions varying from the baseline conditions to obtain scaling parameters. The scaling parameters modify values of the parameters for all logic cells within the library in order to approximate changes in propagation delay through each logic cell resulting from changes in the baseline conditions. In the preferred embodiment, the conditions varying from the baseline conditions includes a change in at least one of operating temperature, power supply voltage and process conditions.

Abstract: An improved digital phase detector is used in a digital phase lock loop having a digitally controlled oscillator which includes a state controller and a counter. One embodiment of the phase detector includes a digital integrator; a first register and a first absolute value function; a second register and a second absolute value function; and a subtractor. In another embodiment the integrator includes a tapped delay line and a parallel summing network. The summing network includes a flow counter. The invention to provide a mechanism for ensuring the symmetry of the integration intervals of an early/late gate phase detector in the presence of phase error and to achieve relaxed timing for the phase error calculation without shortening the integration intervals to less than half a bit time while providing a valid phase error output once for each bit period.

Abstract: A method and apparatus for framing data in digital transmission lines automatically recognizes a framing format. The apparatus preferably includes a frame alignment apparatus that can recognize any one of a number of predetermined framing formats created by framing information on an input signal. The frame alignment apparatus outputs an aligning signal to an output frame counter, which counts the data and framing information on the input signal and outputs a frame synchronization signal according to the framing format. The input signal is also coupled to an output apparatus that outputs the input signal at the clock rate of a terminating apparatus. The frame alignment apparatus preferably includes a plurality of pattern recognizers able to recognize at least one of the framing formats and a storage apparatus for storing counts of successive data and framing information that match a framing pattern. The counts are preferably used to identify the flaming information on the input signal and the flaming format.

Abstract: A combination asynchronous cache system and automatic clock tuning device is disclosed in which the automatic clock tuning device includes at least a pulse generator, a counter, a unit delay tree, a comparing device, and a feedback path. A portion of the feedback path delivers a signal of interest off of the device chip in order that the signal experience the effect of the actual system impedance prior to being returned to the device chip for further manipulation of the signal. A major concept of the automatic clock tuning device is to enable a cache data/tag Write Enable (WE) signal to be clocked off of the falling edge of a delayed version of the System Clock (SCLK). This Delayed Clock (DCLK) signal is automatically delayed by a pre-selected amount each time that the rising edge of the WE signal occurs earlier than the rising edge of the SCLK signal.

Abstract: A memory subsystem for use between a CPU and a graphics controller in a typical small computer system has a cache interface for the CPU and a FIFO interface for the graphics controller. This configuration optimizes the data transfers for both the CPU and the graphics controller, and allows both to operate in a manner generally asynchronous to each other. This caching FIFO provides enhanced performance by matching the interface to the unique data requirements of the devices accessing the data within the caching FIFO. For the CPU, the caching FIFO appears as a normal data cache. For the graphics controller, the caching FIFO appears as a normal dual port FIFO, which optimizes the highly sequential data transfers characteristic of graphics controllers. The simple design of the caching FIFO provides maximum performance for a minimum of gates, making the circuit well-suited to efficient implementation in silicon.

Abstract: A circuit is described for processing an input signal received from a bus of a computer. The circuit includes level identification circuitry to characterize the magnitude of the input signal and to generate a corresponding level identification signal. Level toggle circuitry is connected to the level identification circuitry to process the level identification signal and generate a level hold signal during spurious signal transitions in the input signal. The level toggle circuitry generates a level toggle signal at a predetermined point of the input signal after the spurious signal transitions have subsided. Level hold circuitry, connected to the level identification circuitry and the level toggle circuitry, processes the level identification signal, the level hold signal, and the level toggle signal. During spurious signal transitions in the input signal, the level hold circuitry maintains a high digital circuit output value in response to the level hold signal and the level identification signal.

Abstract: A method for producing a circuit layout comprising the steps of establishing high-level input parameters which identify input/output characteristics and high-level functional parameters of a data path, inputting the input parameters to a compiler, the compiler performing steps of creating a data path netlist by selecting data path components in response to the established high-level input parameters; and automatically selecting control logic for the data path components. The data path netlist is a high-level netlist of Boolean logic which can then easily be translated into a gate level implementation of the circuit layout.

Abstract: The invention accepts user input that describes the circuit elements of a digital circuit and the interconnections between those elements. Based upon the user input, the invention computes the maximum setup and hold times for each data input of the integrated circuit. First, maximum and minimum delays from the clock inputs to the storage elements on the integrated circuit. Similarly, the maximum and minimum delays from the data inputs of the integrated circuit to each level one storage element are determined where a level one storage element is defined as a storage element that has no other storage elements interposed between it and a data input. For each data input/level one storage element pair, the setup time is computed based upon the previously calculated maximum data delay and minimum clock delay and the required setup time for the element. The desired setup time for a data input is the maximum setup time over all the level one storage elements coupled to that data input.

Abstract: A method and apparatus for attenuating jitter in digital signals. A recovered clock is derived from the digital signal and the digital signal is stored in a buffer. The derived clock is input to an input counter which counts a predetermined number of degrees out of phase with an output counter. When the input counter is at a maximum counter value, the output counter value is latched to the address inputs of a ROM look-up table, which outputs a coefficient to a numerically controlled oscillator (NCO). The NCO includes a low frequency portion that adds the coefficient successively to itself and outputs a carry out (CO) signal. A high frequency portion of the NCO receives a high frequency clock and preferably divides down the high frequency clock to a clock frequency which is centered at the desired output frequency. The high frequency portion preferably includes an edge detect circuit that receives the CO signal and adjusts the frequency of the output clock to produce a compensation clock.

Abstract: A method approximates propagation delay through a logic device. Operation of the logic device is divided into a first region and a second region. A boundary between the first region and the second is based on duration of input ramp to the logic device and amount of capacitive load driven by the logic device. For example, the boundary between the first region and the second occurs where for each value of the capacitive load, an output ramp for the logic device is one half complete when the input ramp is complete. When the logic device operates in the first region, a first formula is used to obtain a first value representing delay through the logic device. The first formula varies the first value based on the duration of the input ramp to the logic device and the capacitive load driven by the logic device. When the logic device operates in the second region, a second formula is used to obtain the first value.

Abstract: An IC wafer containing thin oxide is fabricated with at least one pair of antenna structures having identical antenna ratio A.sub.R but different antenna plate areas. Each antenna structure includes connected-together conductive plate regions, one plate formed over thick field oxide and the other plate formed over thin oxide on the IC. Because weak oxide defects occur somewhat uniformly throughout the thin oxide, a larger antenna structure will overlie more weak oxide defects than will a smaller antenna structure. If wafer test leakage current across the larger antenna structure exceeds leakage current across the smaller antenna structure, weak oxide is indicated because the defect is area dependent. By contrast, charge-induced damage is substantially independent of the area of the antenna plates. Because the A.sub.R ratios are constant, charge density is constant in the antenna structure portions overlying the thin oxide.

Abstract: A method and apparatus for attenuating jitter in digital signals. A recovered clock is derived from the digital signal and the digital signal is stored in a buffer. The derived clock is input to an input counter which counts a predetermined number of degrees out of phase with an output counter. When the input counter is at a maximum counter value, the output counter value is latched to the address inputs of a ROM look-up table, which outputs a coefficient to a numerically controlled oscillator (NCO). The NCO includes a low frequency portion that adds the coefficient successively to itself and outputs a carry out (CO) signal. A high frequency portion of the NCO receives a high frequency clock and preferably divides down the high frequency clock to a clock frequency which is centered at the desired output frequency. The high frequency portion preferably includes an edge detect circuit that receives the CO signal and adjusts the frequency of the output clock to produce a compensation clock.

Abstract: A system for providing power to peripheral components associated with a personal computer is disclosed. A local power management unit is located at each controller for a peripheral component in order to provide a distributive power management arrangement. The local power management units communicate with an activity monitor provided in a central power management unit. The foregoing arrangement permits power to be maintained to the bus interface microchips at all times. Deactuation of a controller associated with a peripheral component is accomplished through inhibiting the clock signal produced by the local power management unit associated with the controller. By maintaining power to the bus interface microchips, power leakage through the bus interface microchips is eliminated.

Abstract: An input/output circuit communicates an external input signal to an internal signal and converts an internal signal to an external output signal. In one embodiment, the input/output circuit has a power supply terminal, and an input terminal that is coupled to an output terminal via a conductor. A pull-up circuit is coupled to the power supply terminal and the conductor, and includes a PMOS transistor having an N-well, where the pull-up circuit is configured to selectively pull-up the output signal. A pull-down circuit is coupled to a ground terminal and the conductor, and is configured to selectively pull-down the output signal.

Abstract: A method of manufacturing a microscope probe tip comprises the steps of depositing a first material over a substrate, such as silicon oxide over a silicon substrate using chemical vapor deposition. The first material is patterned to define at least one structural protrusion. During this patterning, the first material is etched back. Then a second material, such as silicon oxide, is deposited over the protrusion using an electron cyclotron resonance (ECR) process, which grows a sloped surface to form the microscope probe tip. In another aspect of the invention, two different resolution Atomic Force Microscope (AFM) probe tips are grown. Then, the cantilevers are coupled together to provide an AFM with two probe tips having different resolutions.

Abstract: A set of circuit specifications including an internal memory structure is developed and then described in a hardware description language that is entered into a computer system. The circuit description is then synthesized on the computer to form a netlist to specify the circuit. From this netlist, an integrated circuit is produced on a semiconductor die, which is then packaged for use. A method for synthesizing a netlist from a hardware description including an internal memory structure includes converting the hardware description into an internal signal list, which contains an indication of the presence of an internal memory structure in the described circuit. For each memory structure indicated, synthesis is performed using a memory cell library, and compatibility between the hardware description for the circuit and the internal memory structure specified is determined. When compatibility is found, the internal memory structure is instantiated into the netlist for the circuit.

Abstract: One or more reinforcement pins are inserted between the lid and base of a sealed integrated-circuit package. The reinforcement pins reinforce a sealing layer between the lid and the base, particularly against shear forces exerted on the sealing layer between the lid and the base of a package. Shorter pins are provided which do not extend through the lid or base. Longer pins are provided which extend through the lid or base, with the ends of the pins being mechanically secured to the lid or base and sealed with solder, glass, or epoxy material.

Abstract: A cache memory controller and method for dumping the contents of a cache directory and a cache data random access memory (RAM) are described. In order to dump the contents of the cache directory, access to the cache data RAM is disabled by disabling the cache controller. Then, address tags within the cache directory are read sequentially from a reserved register. In order to dump the contents of the cache data RAM, new addresses are allocated to data in the cache data RAM. This is done, for example, by blocking writes to the cache data RAM while enabling read access from the cache data RAM and both read and write access to the cache directory. A reserved block of cacheable memory within, for example, the main system memory, is accessed. When the reserved block of cacheable memory is accessed, address tags for addresses of the reserved block of cacheable memory are written into the cache directory; however, data from the reserved block of cacheable memory is not written into the cache data RAM.

Abstract: A method for fabricating an integrated circuit includes the steps of: (a) describing the functionality of an integrated circuit in terms of a behavioral hardware description language, where the hardware description language describes behavior which can be extracted as a state machine; (b) extracting a register level state machine transition table of the state machine from the hardware description language; (c) generating a logic level state transition table representing the state machine from the register level state machine description; (d) creating a state machine structural netlist representing the state machine from the logic level state transition table; and (e) combining the state machine structural netlist with an independently synthesized structural netlist to create an integrated circuit structural netlist including the state machine to provide a basis for chip compilation, mask layout and integrated circuit fabrication.

Abstract: An Isopropyl Alcohol (IPA) tank vapor/liquid phase separator for collecting liquid while still allowing for efficient vapor flow in an IPA tank includes a first row and a second row of spaced-apart coplanar parallel catch trays. Vapor flows upwardly through the openings between the catch trays. The catch trays are arranged so that contaminated IPA condensate falls into either the first or second row of catch trays. In one embodiment, both of the catch trays are upright V-shaped or upright semi-circular-shaped. In another embodiment the catch trays are formed as plates with staggered holes formed therein for upward passage of vapor and for downward collection of condensate.