Abstract: Performance degradation resulting from hot carrier stress is determined using a special test circuit. The test circuit is formed using a string of inverters on an integrated circuit. The string of inverters is connected in series. Every other inverter in the string of inverters uses cascaded transistors so that performance of the inverters with cascaded are not degraded by introduced hot carrier stress. For example, odd numbered inverters are each constructed using cascaded PMOSFETs and cascaded NMOSFETs and even numbered inverters are each constructed using a single PMOSFET and a single NMOSFET. On an input of the string of inverters, a first signal is placed which transitions from logic 0 to logic 1. Propagation delay of the first signal through the string of inverters is measured. Also, a second signal which transitions from logic 1 to logic 0 is placed on the input of the string of inverters. Propagation delay of the second signal through the string of inverters is measured.

Abstract: A look ahead read buffer automatically senses the direction of the read sequence, sets the direction based on the current and previous read addresses, and prefetches data from memory to allow a Host device such as a CPU to read data out of the look ahead read buffer with no wait states, rather than accessing this data directly in slower memory that requires wait states. This read buffer is especially useful in applications such as display controllers that store and retrieve data in sequential format. The display memory may be partitioned into pages, and the read buffer will then determine and set the appropriate direction at page boundaries, and will not change direction within that page of display data. In addition, the read buffer inhibits reads that occur outside of the current page of display data, ignoring the effects of other reads that do not directly affect the display.

Abstract: The ball bump structure of the subject invention provides a hermetically sealed bond pad at the surface of a semiconductor chip. An adhesion pad is formed at the surface of the bond pad. The adhesion pad includes a barrier layer, preferably a titanium/tungsten alloy, and a bonding layer, for example, a sputtered gold layer. A gold ball bump is formed on the adhesion pad. Methods for forming the improved structure herein are also disclosed.

Abstract: The present invention relates to a double ended spring probe ring interface for multiple pin test heads, such as a 120 pin sentry style test head. The double ended spring probe ring is comprised of a non-conductive ring having a plurality of apertures equally spaced along an outer radius of the ring. A plurality of double-ended spring probes are held in the ring by a holding device which is coupled to each spring probe. The holding device holds the spring probe within the ring so as to maintain coplanarity among the spring probes.

Abstract: An integrated circuit with power conservation includes a number of functional blocks, each of which includes digital circuitry and at least one output control line, and a power controller coupled to the control lines. The output control lines develop clock control signals based upon a functional block's knowledge of the direction of data flow. The power controller the reduces power by deactivating functional blocks that are not needed as indicated by the clock control signals. More specifically, a system with power conservation includes a number of functional blocks capable of processing data, each of the functional blocks including a modulated clock input and N+1 clock control lines which reflect the direction of data flow, where N is a number of neighbors of a particular functional block, and a clock controller having an input clock, the clock controller being coupled to the modulated clock inputs and the clock control lines of the functional blocks.

Abstract: A custom netlist editor is provided in which low-level netlist editing procedures may be employed by a user to directly modify a netlist in its native format. The custom netlist editor eliminates the need for user to edit netlist cells by hand or by making a new circuit schematic. More particularly, in accordance with one embodiment of the invention, a netlist is interactively edited on a computer using a plurality of defined netlist editing procedures, the netlist representing a circuit in terms of a hierarchy of cell instances, each cell defining a predetermined circuit component, and signal nets connecting the cell instances. A plurality of user commands are defined, each having as a parameter at least one of the following: a cell name, an instance name, and a signal name. A user is prompted for a command, and a user command is input. The user command is executed by calling at least one of the defined netlist editing procedures.

Abstract: An arithmetic logic unit provides for zero-result prediction so as to eliminate the latency between successive operations (e.g., multiplication and division) when a zero detection is a condition for performance of the second operation. Instead of performing zero detection on the result, zero prediction is performed on the initial or intermediate operands, (e.g., partial products that are summed to generate a product). To this end, zero-prediction logic determines whether or not both of the following conditions are met: 1) either the least significant bits of the addends are the same and the carry-in is zero or the least significant bits of the addends are different and the carry-in is one. 2) for each pair of adjacent bit positions, the four included bits are consistent with addend complementarity. If both conditions are met, a zero result is predicted; otherwise, a non-zero result is predicted.

Abstract: A slip buffer includes a first-in-first-out memory, an input address generating means, an output address generating means, and a slip buffer control logic. The input address generating means generates addresses into which data is read into the first-in-first-out memory. The output address generating means generates addresses from which data is read from the first-in-first-out memory. The slip buffer control logic includes a first latch, a second latch and a slip address generation means. A first boundary address of a first frame boundary is stored in the first latch. The first latch includes a first validity bit which indicates whether the first boundary address is valid, A second boundary address of a second frame boundary is stored in the second latch. The second latch includes a second validity bit which indicates whether the second boundary address is valid.

Abstract: An input buffer for a CMOS integrated circuit comprises parallel pairs of complementary PMOS pull-up and NMOS pull-down transistors. For each NMOS transistor, a polysilicon NMOS gate lead structure includes three sections: a heavily doped gate section, an undoped resistor section, and a heavily doped contact section. The heavily doped contact section is contacted by a metal delivering a logic low voltage (V.sub.SS) so that the NMOS gate is resistively coupled to V.sub.SS. This resistance cooperates with the gate to drain resistance to define a voltage divider between V.sub.SS and V.sub.IN. This voltage divider leaves the gate at a small positive voltage during an electrostatic discharge event. This ensures that all NMOS transistors of a buffer become current bearing before any of them enters second breakdown. This arrangement maximizes input-buffer protection from electrostatic discharge events. The novel NMOS arrangement is readily compatible with CMOS fabrication techniques.

Abstract: An anti-fuse structure formed in accordance with the present invention includes a conductive layer base. A layer of anti-fuse material overlies the conductive base layer. On top of the anti-fuse layer is an insulating layer, in which a via hole is formed to the anti-fuse layer. The lateral dimension of the via hole is less than about 0.8 microns. Provided in the via hole is a conductive non-Al plug which overlies a layer of a a conductive barrier material such as TiN or TiW that contacts the anti-fuse material and overlies the insulating layer. Tungsten is effectively used as the non-Al plug. An electrically conductive layer is formed over the plug and is separated from the conductive barrier material overlying the anti-fuse layer by the plug. The structure is then programmable by application of a programming voltage and readable by application of a sensing voltage, which is lower than the programming voltage.

Abstract: A method and system for programming vROM programmable memories using antifuses fabricated from undoped amorphous silicon as a high resistance link or layer between two metal layers. Whenever a programming voltage higher than a normal operating voltage is applied across the link between the two metal layers, the resistance of the link is reduced by transforming the insulating amorphous silicon into conducting polysilicon. This causes a closed or conductive link to be formed between the two metal layers. In the programming of the vROM, current is actively pumped to the link; and a current measurement or check is made prior to the application of the programming voltage to determine whether the link already has been programmed. Immediately following the application of the programming voltage, the current through the link again is checked to determine proper programming of the link.

Abstract: A behavioral synthesis method for making integrated circuits with built-in self-test (BIST). Base specifications describing base functionality and BIST specifications describing BIST functionality are developed. The base specifications are described in a hardware description language (HDL) to create a base HDL which is input into a digital computer system. Utilizing both the base specifications and the BIST specifications, a BIST HDL is created on the digital computer system. A netlist is synthesized on the computer system from both the base HDL and the BIST HDL. Thereafter, a digital integrated circuit is produced as specified by the netlist. An advantage of the present invention is the description of BIST circuitry at the HDL level of abstraction instead of at the netlist level. By automatically generating BIST HDL given BIST specifications and base circuit specifications, a circuit designer is relieved of the complications of gate level manipulations to insert a BIST description into a netlist.

Abstract: A purely digital randomizer system generates an undeterministic data block using standard cell library units and includes a random number generator. The generator preferably includes at least two metastable blocks that each include a plurality of D-type flip-flops. Each flip-flop is coupled to a dedicated free-running oscillator whose frequency is based on a relative prime number for each frequency leg. Each of the D-type flip-flops is also coupled to receive a common jitter clock signal. The flip-flops are thus forcibly operated in a metastable state by intentionally violating the flip-flop set-up or hold time margins of incoming data relative to the jitter clock. To further maximize entropy, the flip-flop outputs are exclusively `OR`d ("EX-OR'd") and then passed through first and second shift registers of uneven and preferably even and odd bit lengths. Preferably each shift register includes at least one metastably-operated D-type flip-flop, to further promote randomness.

Abstract: The present invention relates to a spring probe contactor for testing BGA devices. The spring probe contactor is comprised of a plurality of spring probes for providing a connection between a BGA device to be tested and a DUT board. The plurality of spring probes are held within a contactor block having a plurality of apertures therethrough. The apertures are wide enough to hold a single spring probe within the contactor block without the spring probe coming into contact with the contactor block. A retaining plate is coupled to the contactor block for holding the plurality of spring probes within the contactor block. The retaining plate has a raised portion thereon which limits the compression of the plurality of spring probes when a BGA device is placed in the spring probe contactor.

Abstract: An integrated circuit with random access memory (RAM) and a built-in self tester for the RAM is disclosed. The built-in self tester includes a RAM BIST controller, a comparator, and a BIST I/O. The RAM BIST controller controls the RAM during a test where the RAM includes data, address, and control lines. The comparator is responsive to outputs of the RAM BIST controller and the RAM and develops an error signal. The BIST I/O is responsive to outputs of the comparator and has an output coupled to one of the I/O ports. The BIST I/O is further capable of storing an address of a data storage location in the RAM that malfunctions during the test and outputting the address via an integrated circuit I/O port.

Abstract: A multilevel antifuse structure characterized by a substrate, a first antifuse structure formed above the substrate, and a second antifuse structure formed above the first antifuse structure. The first antifuse structure preferably includes a first conductive layer, a first antifuse layer disposed over the first conductive layer, a first dielectric layer disposed over the first antifuse layer and provided with a first via hole, and a first conductive via formed within the first via hole. The second antifuse structure preferably includes a second conductive layer, a second antifuse layer disposed over the second conductive layer, a second dielectric layer disposed over the second antifuse layer and provided with a second via hole, and a second conductive via formed within the second via hole. Preferably, the first antifuse layer and the second antifuse layer are patterned into a plurality of antifuse regions which are either vertically aligned or vertically staggered with respect to each other.

Abstract: A method for producing a circuit layout comprising the steps of establishing high-level input parameters which identify input/output characteristics and high-level functional parameters of a data path, inputting the input parameters to a compiler, the compiler performing steps of creating a data path netlist by selecting data path components in response to the established high-level input parameters; and automatically selecting control logic for the data path components. The data path netlist is a high-level netlist of Boolean logic which can then easily be translated into a gate level implementation of the circuit layout.

Abstract: An adapter unit configurable for testing ICs having different power and ground contact configurations is customized for one of such configuration and mounted on a load board having first and second plurality of signal contacts, wherein respective pairs of the first and second plurality of signal contacts are connected to both a contact of the IC and a test channel from an IC tester. The adapter unit is mounted on the load board making contact with the first plurality of signal contacts, while a DUT board holding the IC is mounted on the load board making contact with the second plurality of signal contacts. The adapter unit includes a plurality of signal contacts respectively connected to the first plurality of signal contacts of the load board, a power bus ring connected to a power line provided by the IC tester, and a ground bus ring connected to a ground line from the IC tester.

Abstract: A hardware cursor is implemented on a typical video display controller, and uses an unused portion of video RAM as cursor memory to store the cursor information. Since the cursor memory may be located at any unused location of video RAM, it is a virtual hardware cursor since the location of cursor data may changed as required. The operation of the cursor may be programmed, monitored and controlled via control registers. The hardware cursor monitors the video control signals to determine when to put out cursor data rather than directly outputting pixel data. The hardware cursor fetches the appropriate cursor data from the cursor memory in the video RAM during the horizontal nondisplay period just prior to a line of display data that should contain cursor data. The hardware cursor then monitors the pixel stream and outputs unchanged pixel data until a cursor location is reached, at which time the hardware cursor outputs a logical combination of cursor data, cursor color, and pixel value.

Abstract: A coating method for detecting the presence of contaminants carried by a liquid that is applied as a coating on a workpiece. A tube guides the liquid along a flow path to the workpiece. A light source illuminates the liquid along the flow path with an optical fiber or other light carrier, and light is scattered by any contaminants present in the liquid. Light scattered by the contaminant particles is more intense than light scattered by the other liquid particles, and this brighter scattered light is detected by a light detector positioned adjacent to the fluid flow path. The coating system is particularly well suited for use in a spin-on coating process that applies a liquid, such as a photoresist material or a dielectric material, to a semiconductor wafer or other workpiece that is secured to a rotating turntable and rotated to receive a coating of the liquid.