Abstract: The present invention is an ultrasonic transducer slurry dispensing device and method for efficiently distributing slurry. The present invention utilizes ultrasonic energy to facilitate efficient slurry application in a IC wafer fabrication process to permits reduced manufacturing times and slurry consumption during IC wafer fabrication. In one embodiment a chemical mechanical polishing (CMP) ultrasonic transducer slurry dispenser device includes a slurry dispensing slot, a slurry chamber coupled and an ultrasonic transducer. The slurry chamber receives the slurry and transports it to the slurry dispensing slots that apply slurry to a polishing pad. The ultrasonic transducer transmits ultrasonic energy to the slurry.

Abstract: An interface system for testing and verifying the design of an ASIC at different levels of abstraction, wherein the ASIC includes a logic entity and a processor entity. The system of the present invention is embodied as software which executes within a computer system. The software, when executed by the computer system, causes the computer system to implement a model of the ASIC, a simulator, and a test interface. The model of the ASIC is embodied in HDL (Hardware Description Language) and includes a logic entity and a processor entity. The simulator is adapted to test the model. The test interface interfaces the model with the simulator. The test interface includes a simulator portion and a model portion. The simulator portion is coupled to the simulator. The model portion is embodied in HDL and is coupled to both the logic entity and the processor entity. The model portion and the simulator portion are coupled to exchange information.

Abstract: An integrated circuit includes a substrate with doped regions, a patterned polysilicon layer defining contacts and local interconnects, a submetal dielectric, a two-metal layer metal interconnect structure with an intermetal dielectric layer, and a passivation layer. Like the dielectric layers, the passivation layer is optically transparent, thick, and planarized. Because of this, laser energy can be directed through the passivation layer to fuse two conductors of the top metal layer without delaminating the passivation layer. In addition, laser energy is directed through the passivation layer and the intermetal dielectric to fuse pairs of conductors in the lower metal layer. Thus, the present invention provides for reliable convenient circuit modification without disturbing dielectric and exposing metal features to moisture and other contaminants.

Abstract: The present invention provides methods of synchronization, personal handy-phone system stations, and phase lock loops. Synchronization of a personal handy-phone system station with a telecommunication network, and another communication station are provided. One method of synchronization comprises: providing a counter configured to generate a plurality of counter values; storing a first counter value; detecting a reference event; latching a second counter value responsive to the detecting of the reference event; comparing the first counter value and the second counter value to detect phase drift; and compensating for phase drift responsive to the comparing.

Abstract: Thickness of a wafer is monitored during grinding. A conductive plate is located below the wafer during grinding. One or more capacitive sensors are located above the wafer during grinding. A monitoring device monitors capacitance of the conductive plate and the capacitive sensor.

Abstract: The present invention is a vacuum removal system for removing polishing by-products from the surface of a polishing pad in a chemical mechanical polishing (CMP) machine used to polish wafers. The vacuum removal system includes a vacuum removal nozzle which is adapted to dislodge and remove polishing by-product particles from a textured surface of a polishing pad through the application of suction. The vacuum removal nozzle is connected to a mounting attachment. The mounting attachment is mounted on the polishing machine and is adapted to maintain close proximity of the vacuum removal nozzle with the textured surface of the polishing pad. A vacuum line is connected to the vacuum nozzle to convey a vacuum to the vacuum nozzle and to receive the polishing by-product particles from the vacuum nozzle. A vacuum source is connected to the vacuum line to generate the vacuum used by the system.

Abstract: Power-on-reset logic is included within an integrated circuit. The power-on-reset logic includes a power-on-reset cell. The power-on-reset cell causes a reset signal to be issued upon a power signal being connected to the integrated circuit. The power-on-reset cell includes a power down input connected to a power-down line. When a power-down signal is placed on the power-down line, the power-on-reset cell is inactivated so that the power-on-reset cell does not cause the reset signal to be issued upon the power signal being connected to the integrated circuit. The power-on-reset logic also includes a logic block connected to the power-down line and to a system clock. The logic block issues a reset when the power-down signal is placed on the power-down line and the system clock is active. For example, the logic block is a delay (D) flip-flop having a D input connected to the power down line and a clock input connected to the system clock.

Abstract: A method is provided for reducing contact resistances in semiconductors. In the use of fluorocarbon plasmas during high selectively sub-quarter-micron contact hole etching, with the silicon dioxide(SiO2)/silicon nitride(Si3N4)/silicide(TiSix) layers, polymerization effects have been discovered to be crucial. The process includes using a high etch selective chemistry, to remove SiO2 first, then switching to another chemistry with high selectivity of Si3N4-to-TiSix. To obtain good etch selectivity of SiO2-to-Si3N4, fluorocarbon plasmas containing high C/F ratio are employed. This results in the formation of reactive unsaturated polymers which stick easily to contact hole sidewalls and bottoms. Fluorine from the polymer was discovered to severely degrade the etch selectivity of Si3N4-to-TiSix. Different polymer removing methods to restore etch selectivity of Si3N4-to-TiSix are provided which can be applied to any highly selective etching of oxide versus nitride.

Abstract: A method and apparatus for programmable read only memory with high speed differential sensing at low operating voltage. In one embodiment, a programmable memory cell is comprised of word line, a bitline, and a transistor. The transistor, representing a single binary digit (bit), has a gate coupled to a word line, a drain coupled to a bitline, and a source capable of being programmed to provide a logic level of 0 and a logic level of 1. By programming the source of the transistor, the bitline approximately equal capacitance for both logic level 0 and logic level 1 states.

Abstract: A dynamic error correction system for a bi-directional digital data transmission system. The transmission system of the present invention includes a transmitter adapted to encode information into a signal. A receiver receives the signal and decodes the information encoded thereon. The signal is transmitted from the transmitter to the receiver via a communications channel. A signal quality/error rate detector is coupled to the receiver and is adapted to detect a signal quality and/or an error rate in the information transmitted from the transmitter. The receiver is adapted to implement at least a first and second error correction process, depending upon the detected signal quality/error rate. The first error correction process is more robust and more capable than the second error correction process. The receiver coordinates the implemented error correction process with the transmitter via a feedback channel.

Abstract: Accordingly, exemplary embodiments of the present invention are directed to single poly flash EEPROM cells which avoid the drawbacks of conventional two poly stacked gate cells, and which are easily integrated with high performance logic technologies. An exemplary two transistor flash-EEPROM memory cell array comprises a plurality of these flash EEPROM cells, each having a select transistor with a bit line and a word line, where the select transistor is in series with a floating gate transistor. The floating gate transistor has a thin tunneling oxide formed on a textured monocrystalline substrate. The floating gate is also formed over a heavily doped region in the substrate which forms a coupling line capacitively coupled to the floating gate, and which performs a tunneling function.

Abstract: The present invention provides methods of forming a semiconductor workpiece. One method of forming a semiconductor device in accordance with the present invention includes: providing a semiconductor workpiece; forming a via within the semiconductor workpiece, the via including plural sidewalls joining a bottom surface at respective plural corners; first sputtering a process layer upon at least a portion of the bottom surface using ionized metal plasma physical vapor deposition; and following the sputtering of the process layer, second sputtering at least some of the process layer towards the corners within the via.

Abstract: The present invention comprises a system for implementing pseudo delayed transactions through a bridge in order to guarantee access to a shared device. The system of the present invention functions in a computer system having a plurality of busses, including a first bus on one side of a bridge and a second bus on another side of the bridge. A first initiator device and a second initiator device are coupled to the first bus. The first and second initiator devices are both adapted to request ownership of the first bus and receive a respective first and second grant signal responsive thereto. A target device is coupled to the second bus. The bridge is coupled to the first bus and the second bus. The bridge is adapted to implement data transactions between the target device and the first device or the second device.

Abstract: A system and method for preventing address aliasing when using a single address cycle to transmit a target address in a computer system that includes target devices having addresses of different ranges. The computer system comprises a bus, an initiator device coupled to the bus, a first target device coupled to the bus, and a second target device coupled to the bus. The first target device has a first address range comprising a plurality of bits, and the second target device has a second address range comprising a fewer number of bits than the first address range. The initiator device transmits a signal indicating the size of the target address and also separately transmits in a single address cycle the target address. The second target device disables its address decode logic in response to the signal from the initiator device provided that the size of the target address is greater than the second address range.

Abstract: A method and apparatus for programmable read only memory with high speed differential sensing at low operating voltage. In one embodiment, a programmable memory cell is comprised of word line, a bitline, and a transistor. The transistor, representing a single binary digit (bit), has a gate coupled to a word line, a drain coupled to a bitline, and a source capable of being programmed to provide a logic level of 0 and a logic level of 1. By programming the source of the transistor, the bitline approximately equal capacitance for both logic level 0 and logic level 1 states.

Abstract: A method of designing a reset circuit for a digital integrated circuit (IC) layout is described. The reset circuit is designed with the intention of making it visually non-detectable in the digital IC layout by implementing the reset circuit entirely in digital elements and then using standardized digital layout cells and routing such that the reset circuit is essentially non-discernible from the digital circuitry of the IC device layout. In addition, circuit elements are designed using devices having dimensions that are essentially the same as typical digital devices in the digital IC layout.

Abstract: A method and a system implement a circuit design in an integrated chip. A floorplan of the circuit design is arranged at a high level of abstraction. The design is synthesized based on the floorplan, and the synthesized design is laid out physically on the integrated circuit.

Abstract: A chemical-mechanical-polishing system having a slurry distribution system, a polisher, a deionized water supply, and a drain, includes a slurry filtration system. The filtration system has two filters for alternately filtering particles in slurry and being backflushed with deionized water. Two input valves have input ports connected to the slurry distribution system and output ports respectively connected to the filters for filtering. Two output valves have input ports respectively connected to the filters for receiving filtered slurry and output ports connected to the polisher. Two backflush valves have input ports connected to the deionized water supply and output ports respectively connected to backflush with deionized water; the output ports are also respectively connected to the input ports of the two output valves. Two drain valves have input ports respectively connected to the filters for receiving backflushed fluid and output ports connected to the drain.

Abstract: A voltage-buffer circuit for changing an input signal at a first voltage range to an output signal at a second voltage range. In one embodiment, the voltage-buffer circuit is comprised of an input lead for receiving an input signal at a first voltage range, a plurality of transistors coupled to the input lead, and an output lead coupled to the plurality of transistors. The purpose of the transistors is to convert the input signal at the first voltage range to an output signal at a second voltage range. The output lead is for receiving the output signal at the second voltage range from said plurality of transistors. The plurality of transistors are arranged into a plurality of stages, with at least one of the transistors having a gate oxide of a first thickness and at least one of the transistors having a gate oxide of a second thickness, where the first thickness is less than said second thickness.

Abstract: A technique for conserving digital memory space is disclosed. This technique includes sequentially transmitting a first address and a second address on a first bus coupled to a FIFO memory. The first address is stored in the memory and compared to the second address to determine a first value corresponding to a difference between the first and second addresses. This first value is written in the memory to represent the second address and has a bit size smaller than the second address. A method to decode the first value to regenerate the second address is also disclosed. These techniques may be further enhanced by only storing an address in a sequential access memory when it differs from the most recently stored address in the memory.