Abstract: A semiconductor wafer polishing method comprises forming at least one alignment mark within an alignment area on a semiconductor wafer, forming a layer to be polished over the wafer, the layer being formed to be generally elevationally higher proximately about and surrounding the alignment area than within the alignment area, and polishing the layer. According to another aspect, a semiconductor wafer includes an alignment marking area formed relative to a surface of the wafer. At least one alignment mark is provided within the alignment area. A structure is formed about the alignment marking area and extends from the wafer surface a greater elevation than any elevation from such surface from which the alignment mark extends. Furthermore, a layer of material to be polished is provided over the structure to cause the material to be polished to be elevationally higher over the structure than over the alignment mark.

Abstract: A method for remotely updating software code of personal handy phone system equipment. The present invention enables a remotely located control terminal to update stored software code within a distant portable station or cell station of the personal handy phone system. Specifically, by coupling a control terminal to the existing communication network of a personal handy phone system, the control terminal is able to communicate with portable stations and cell stations. To update the software code of a specific portable station or cell station, the control terminal first establishes communication with that particular device by sending an unique preparatory signal addressed to it. The addressed device receives the unique preparatory signal and checks the validity of it. If the addressed device determines the unique preparatory signal is valid, it transmits a unique verification signal addressed to the control terminal indicating that it is ready to receive the updated version of the software code.

Abstract: Exemplary embodiments are directed to providing a flash EEPROM technology which is compatible with deep submicron dimensions, and which is suitable for straightforward integration with high performance logic technologies. Unlike known technologies, exemplary embodiments provide a reduced cell area size in a split gate cell structure. An exemplary process for implementing a flash EEPROM in accordance with the present invention involves growing a tunneling oxide in a manner which reduces tunneling barrier height, and requires minimum perturabition to conventional high performance logic technologies, without compromising logic function performance.

Abstract: A circuit for programmably generating a delay in a frequency monitor. In one embodiment, the circuit includes a delay cell. A delay cell controller is coupled to the delay cell. The delay cell controller is adapted to selectively control whether the delay cell is activated such that the frequency monitor can be programmably configured to have a selected delay associated therewith.

Abstract: A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas.

Abstract: A multi-platen chemical-mechanical polishing system is used to polish a wafer. The wafer is polished at a first station. During polishing, an endpoint is detected. The endpoint is detected by generating optical radiation by a first light source. The first optical radiation travels through a translucent area in a surface of a first platen and travels through a first polishing pad. After being reflected by the wafer, the optical radiation returns through the first polishing pad through the translucent window to a first optical radiation detector. The first polishing pad has a uniform surface in that no part of the surface of the first polishing pad includes transparent material through which non-scattered optical radiation originating from the first light source can pass and be detected by the first optical radiation detector. Optical radiation that travels through the first polishing pad and is detected by the first optical radiation detector is haze scattered by inclusions within the first polishing pad.

Abstract: A digital phase shift amplification and detection system and method for amplifying and detecting a phase shift. A signal is applied to a digital phase shift amplifier including a flip flop operated in the metastable region in which the applied signal transitions at a relatively close time to a trigger in the clock signal of the flip flop. The digital phase shift amplification and detection system and method amplifies any timing changes in the signal. The amplified signal is fed into a detection circuit configured to detect timing delays in the amplified signal. A signal is applied to a digital phase shift amplifier including a flip flop operated in the metastable region which amplifies any timing changes in the signal. The amplified signal is fed into a detection circuit configured to detect the amplified timing differences in the amplified signal as a result of a relatively smaller timing change in an input signal.

Abstract: An integrated circuit workpiece is provided having a polysilicon transistor gate member extending from a substrate. A pair of oxide spacers are formed on opposing sides of the gate member and a metal layer is deposited on the workpiece. The workpiece is heated to form a silicide region on the gate member and on selected regions of the substrate. A surface profile for each of the spacers is provided which has a progressively steeper slope from a rounded upper shoulder portion to a lower wall portion to control thickness of the metal layer on the gate member relative to thickness on the spacers. Formation of the spacers may include plasma etching with a gas mixture having from about 1 to about 20% molecular oxygen to steepen a slope of the surface profile of each of the spacers. Further, shaping of the spacers may be utilized to establish a ratio of the minimum thickness on the gate member to the minimum thickness on each spacer of at least about 2.5 to reduce silicide bridging of the spacers.

Abstract: A method for determining translation portion of misalignment error in a stepper. In one embodiment, the method comprises a series of steps in a stepper, starting with the step of receiving a wafer in the stepper. In another step a first pattern, including an error-free fine alignment target, is created on the wafer. Next, the wafer is realigned in the stepper using the error-free fine alignment target. Then a second pattern is created on the wafer overlaying said first pattern. In another step, the translational error between the first pattern and the second pattern is measured.

Abstract: A system for intelligent C-plane switching in the digital enhanced cordless telecommunications (DECT) system. The present invention includes a system that enables fast C-plane transmission mode during cordless telephone voice connections within the digital enhanced cordless telecommunications (DECT) system without degrading the voice quality. In order to perform this fast C-plane transmission mode during voice connections, one embodiment of the present invention, located within a cordless telephone handset, utilizes a silence detector circuit to determine the periods of silence within the voice data transmitted through the U-plane. By determining the periods of silence within the U-plane voice data, the present invention is able to direct the control data to be transmitted through the fast C-plane during the periods of silence.

Abstract: An address decoder includes a plurality of address decoder modules. Each address decoder module has a select line for each of a plurality of devices. Each of a plurality of XOR combination circuits performs a logic XOR function of all select lines for a single device from the plurality of devices. State control within the address decoder activates one address decoder module at a time.

Abstract: Voice recording and playback mode using the G.726 half-rate within the personal handy phone system (PHS). When a portable station within the PHS operates as a voice recorder (e.g., functioning as an answering machine), a cost effective system in accordance with the present invention is adapted to compress and store received voice/sound signals in order to increase the usage of limited memory resources provided within the portable station. The present invention also enables previously compressed and stored voice/sound signals to be decompressed and played back in various portable station playback modes. Specifically, the portable station receives a voice/sound signal in a full rate (e.g., 32 kilobits-per-second) 4-bit adaptive differential pulse code modulation (ADPCM) data format in compliance with the International Telecommunication Union (ITU) recommendation G.726.

Abstract: A method and apparatus for programmable read only memory with high speed differential sensing at low operating voltage. In one embodiment, a programmable memory cell is comprised of word line, a bitline, and a transistor. The transistor, representing a single binary digit (bit), has a gate coupled to a word line, a drain coupled to a bitline, and a source capable of being programmed to provide a logic level of 0 and a logic level of 1. By programming the source of the transistor, the bitline approximately equal capacitance for both logic level 0 and logic level 1 states.

Abstract: A flip-chip semiconductor device with generic bump patterns formed on a semiconductor substrate and having optimized electrical performance is provided. In a preferred embodiment, the flip-chip semiconductor device includes a semiconductor substrate on which active elements are formed and which has a surface having a plurality of peripheral portions, the active elements including Input/Output (I/O) circuitry and logic circuitry, a first power supply wiring and a first ground wiring disposed in the semiconductor substrate, a signal wiring disposed in the semiconductor substrate, and a first plurality of bumps arranged on the plurality of peripheral portions and selectively used for coupling the semiconductor substrate to a second substrate. The first plurality of bumps are arranged in a matrix pattern of 6 rows by n columns. Bumps in predetermined locations in the matrix are selectively coupled to the first power supply wiring and the first ground wiring.

Abstract: A chemical-mechanical-polishing system having a slurry distribution system, a polisher, a deionized water supply, and a drain, includes a slurry filtration system. The filtration system has two filters for alternately filtering particles in slurry and being backflushed with deionized water. Two input valves have input ports connected to the slurry distribution system and output ports respectively connected to the filters for filtering. Two output valves have input ports respectively connected to the filters for receiving filtered slurry and output ports connected to the polisher. Two backflush valves have input ports connected to the deionized water supply and output ports respectively connected to backflush with deionized water; the output ports are also respectively connected to the input ports of the two output valves. Two drain valves have input ports respectively connected to the filters for receiving backflushed fluid and output ports connected to the drain.

Abstract: A method of using polish stop film to control dishing during copper chemical mechanical polishing. In one embodiment, the method comprises several steps. One step involves depositing a polish stop layer above a metal layer disposed on a semiconductor wafer. Another step involves placing the semiconductor wafer onto a polishing pad of a chemical mechanical polishing machine. A further step involves removing the metal layer of the semiconductor wafer and also preferentially removing the polish stop layer using a chemical mechanical polishing process. The benefit of the polish stop layer is to prevent dishing of the metal layer within the trench. Another step involves ceasing the chemical mechanical polishing process when the metal layer is removed from desired areas of the semiconductor wafer and the semiconductor wafer is substantially planar.

Abstract: A system for dislodging by-product agglomerations from a polishing pad of a chemical mechanical polishing (CMP) machine. The present invention is used in conjunction with a CMP machine that polishes semiconductor wafers. Specifically, an embodiment of the dislodging system in accordance with the present invention includes a megasonic nozzle which is adapted to effectively dislodge polishing by-product agglomerations and particles from the grooves and micro-pits of the surface of a polishing pad through the application of an output stream of extremely agitated fluid (e.g., deionized water). One embodiment of the megasonic nozzle in accordance with the present invention includes two piezoelectric transducers which operate at a resonant frequency to produce the extremely agitated stream of fluid. A fluid line is connected to the megasonic nozzle and a fluid source in order to convey fluid to the megasonic nozzle.

Abstract: Computer-implemented methods and apparatus for extracting and computing parasitic capacitance values and capacitances respectively, from a physical design of an integrated circuit are described. In one embodiment, the physical design comprises a plurality of layered conductors which are disposed within a first dielectric material. At least one conductor of the plurality of conductors is identified, and for the identified conductor, the first dielectric material is replaced for calculational purposes with a second (fictitious) dielectric material having a dielectric constant which is higher than the dielectric constant of the replaced dielectric material. In general, the second dielectric may have a different dielectric constant for each identified layer or elevation. Parasitic capacitance values are then computed for the integrated circuit. In a preferred embodiment, spaced-apart conductors at a common substrate elevation are identified, and a distance between the conductors is determined.

Abstract: The present invention provides stimuli generators, methods of analyzing a cell, methods of generating at least one stimuli, and methods of characterizing delay of a cell. One method of analyzing a cell in accordance with the invention includes providing a truth table which includes plural lines defining the logical behavior of a cell, the truth table comprising stimulus for application to the cell and output information generated by the cell responsive to applied stimulus; providing a preselected condition; and selectively extracting at least one stimuli from the truth table responsive to the preselected condition.

Abstract: A method and system that enables an automatic delay setting within a wireless local loop system. The present invention determines the transmission distance time delay existing between a base station and a personal station by employing the communication interface that is utilized between them. The main reason for determining the transmission time delay caused by large transmission distances (e.g., over 300 meters) existing between base stations and personal stations is to compensate for it. Once the transmission distance time delay is known, the personal station utilizes that value to compensate for it. Specifically, the present invention directs a base station to transmit a control signal to a personal station. The personal station receives the control signal and transmits a signal to the base station. The base station determines if it started to receive the signal from the personal station later than it expected the signal to arrive, assuming close proximity of the two stations.