Abstract: Comparators, memory devices, comparison methods and memory reading methods are provided. One aspect provides a comparator including an input stage having a data input adapted to receive a data voltage signal, a reference input adapted to receive a reference voltage signal, and a plurality of current sources individually coupled with one of the data input and the reference input and individually configured to convert one of the data voltage signal and the reference voltage signal to a differential current signal and to output the differential current signal; and a comparator stage including a plurality of inputs configured to receive the differential current signals from the input stage and the comparator stage being configured to compare the differential current signals and to output an output signal indicative of a comparison of the differential current signals.

Abstract: A system and method for eliminating unnecessary data transfers (e.g., null data phase transfers) in a computer system. The computer system comprises a bus, a target device coupled to the bus, and an initiator device coupled to the bus. The initiator device is adapted to transfer a data byte and a signal corresponding to the data byte over the bus to the target device, wherein the signal is equal to a first value to indicate that the target device is to accept the data byte and the signal is equal to a second value to indicate that the target device is to disregard the data byte. The initiator device is further adapted to decode the signal for each of a plurality of data bytes. The initiator device withholds transferring a subset of the data bytes to the target device when the signal corresponding to each of the data bytes in the subset is equal to the second value, thereby eliminating unnecessary data transfers.

Abstract: A system and method for using single address cycles and eliminating dual address cycles to transmit a target address in a computer system. The computer system comprises a bus, a central processing unit coupled to the bus, an initiator device coupled to the bus, and a target device coupled to the bus. The target device comprises a first configuration register which is adapted to use a configuration bit to indicate an address range of the target device. The central processing unit interrogates the first configuration register and communicates the address range indicated by the configuration bit to the initiator device. The initiator device comprises a second configuration register which is adapted to use a configuration bit to register the address range of the target device.

Abstract: A multi-platen chemical-mechanical polishing system is used to polish a wafer. The wafer is polished at a first station. During polishing, an endpoint is detected. The endpoint is detected by generating optical radiation by a first light source. The first optical radiation travels through a translucent area in a surface of a first platen and travels through a first polishing pad. After being reflected by the wafer, the optical radiation returns through the first polishing pad through the translucent window to a first optical radiation detector. The first polishing pad has a uniform surface in that no part of the surface of the first polishing pad includes transparent material through which non-scattered optical radiation originating from the first light source can pass and be detected by the first optical radiation detector. Optical radiation that travels through the first polishing pad and is detected by the first optical radiation detector is haze scattered by inclusions within the first polishing pad.

Abstract: A method and system that enables real-time peripheral devices to be connected to a computer system utilizing Universal Serial Bus architecture. The present invention empowers the computer system to perform an accurate determination of the moment in time a predetermined event occurred within a real-time peripheral device by utilizing the start of frame pulse transmitted from a USB host controller to peripheral devices connected to it. When a predetermined event occurs within a peripheral device, a first timer within the peripheral device starts incrementing to determine the amount of time that elapses until the next start of frame occurs. Once the next start of frame occurs, the first timer stops incrementing and stores the time before start of frame value. Every start of frame pulse causes a second timer located within the USB host controller to start incrementing.

Abstract: A target configuration prediction system that provides an initiator coupled to a bus system with a prediction of the configuration type of a target. The present invention stores information regarding the address and configuration of targets and utilizes this information to predict the address of a target an initiator is currently attempting to access. The prediction is based upon the proximity of stored target addresses to a target address an initiator is currently trying to access and the probability that targets with addresses within certain ranges are the same target configuration type. The configuration type is determined by initiator component logic during an initial attempt at accessing a target and a status bit indicating the configuration type is stored in a status bit component.

Abstract: A flat, thin decoupling capacitor is disposed inside an integrated circuit device in a coplanar relationship with a semiconductor chip and a bonding element. When connected to the power and ground plane of a device substrate or in a leadframe device, the decoupling capacitor is positioned close to the semiconductor chip to substantially reduce ground bounce and crosstalk from the semiconductor chip. When the decoupling capacitor is positioned to locate the semiconductor chip between itself and the device substrate or leadframe device, the decoupling capacitor shields electromagnetic interference from the semiconductor chip.

Abstract: The present invention relates to a method and device for providing CMOS logic which can be operated at various operating voltages, without resulting in unbalanced operation of n-channel and p-channel CMOS transistors. In accordance with the present invention, CMOS circuitry can be provided that is operable over a range of voltages (e.g., a range from below 3 volts to a range over 5 volts) without producing unbalanced operation of n-channel and p-channel transistors. Thus, integrated circuits formed in accordance with the present invention can be operated at different voltage power sources without requiring a redesign or relay out of the integrated circuit. In accordance with the present invention, CMOS transistors can be fabricated without increased fabrication complexity to provide transistors which operate within a relatively safe region of their operating characteristics and which operate with a speed that is unaffected by the reduced voltage supply (i.e.

Abstract: Copper is the bulk interconnect metal in the manufacture of an integrated circuit in accordance with the damascene process. When copper is exposed through via apertures, carbon monoxide and hydrogen are used as reduction agents to convert black copper oxide to red copper oxide and the red copper oxide to copper. The integrated circuit is then transferred in a high vacuum to a sputter chamber so that re-oxidation does not occur before tantalum barrier metal can be deposited. As a result, a good tantalum-copper electrical contact can be made without risking embedding copper in oxide sidewalls (whence it could migrate to active circuit regions and impair device reliability).

Abstract: A method of using films having optimized optical properties for chemical mechanical polishing (CMP) endpoint detection. Specifically, one embodiment of the present invention includes a method for improving chemical mechanical polishing endpoint detection. The method comprises the step of depositing a dielectric layer over a reflectance stop layer. The reflectance stop layer is disposed above a component that is disposed on a semiconductor wafer. During a determination of the thickness of the dielectric layer using a reflected signal of light, the reflectance stop layer substantially reduces any light from reflecting off of the component. Therefore, the present invention provides a method and system that provides more accurate endpoint detection during a CMP process of semiconductor wafers. As a result of the present invention, an operator of a CMP machine knows precisely when to stop a CMP process of a semiconductor wafer.

Abstract: The present invention provides a method of generating a data stream comprising: generating a first slot having a first data field; generating a second slot; and providing the second slot within the first data field of the first slot. The present invention additionally provides methods of validating an integrated circuit and communicating a data stream.

Abstract: A primary layer deposited over a secondary layer is planarized. A chemical mechanical polishing process is performed using a slurry which targets the primary layer. Then, chemical etching is performed using a chemical wet etchant which targets the secondary layer. The method is used, for example, when making connections to a lower layer through an insulating layer. Plug holes are formed through the insulating layer to the lower layer. Then the secondary layer is deposited. The secondary layer acts as a barrier layer or a glue layer.

Abstract: A distributed firewall is utilized in conjunction with a memory-mapped serial communications interface such as that defined by the IEEE 1394 specification to permit secure data transmission between selected nodes over the interface. The distributed firewall incorporates security managers in the selected nodes that are respectively configured to control access to their associated nodes, thereby restricting access to such nodes to only authorized entities. Furthermore, encrypted transmissions may be supported to restrict unauthorized viewing of data transmitted between the selected nodes over the interface. Implementation of the distributed firewall does not modify any critical specifications for the memory-mapped communications interface that would prevent the selected nodes from residing on the same interface as other nodes that adhere to such specifications but that do not support secure data transmission.

Abstract: A method is presented in which nitrogen-based gas in incorporated in polysilicon gate re-oxidation to improve hot carrier performance. A gate oxide layer is formed. Gate material is deposited on the gate oxide layer. The gate material is etched to form a gate structure. The gate oxide layer and the gate are re-oxidized. During re-oxidation, nitrogen-based gas is introduced to nitridize re-oxidized portions of the gate oxide layer.

Abstract: A process for making an integrated circuit is disclosed. This technique includes electrically interconnecting a pair of adjacent transistors positioned along a semiconductor substrate by coating with an oxide layer, planarizing the layer, then forming a trench exposing a contact region for each transistor. This trench is filled with a metal, such as tungsten to provide an electrical interconnection of the contact regions. The metal is then planarized to be approximately coplanar with the planarized oxide layer. Metal gate electrodes are formed at the same time as the interconnection. Additional processing includes depositing an IMO layer over the planarized metal and oxide and defining additional interconnections through the IMO layer.

Abstract: The present invention includes an integrated circuit package, a ball-grid array integrated circuit package, a method of packaging an integrated circuit, and a method of forming an integrated circuit package. According to one aspect, the present invention provides an integrated circuit package including a substrate including a first surface, a second surface and a plurality of conductors, the first surface includes a plurality of conductive pads adapted to couple with a plurality of corresponding bond pads of a semiconductor die, and the conductors being configured to couple the conductive pads with the second surface; and a plurality of conductive bumps coupled with the second surface of the substrate and electrically coupled with respective conductors, the conductive bumps being formed in an array including a plurality of power bumps and signal bumps, and the signal bumps being individually positioned immediately adjacent at least one power bump.

Abstract: A method for preparing a semiconductor substrate for subsequent silicide formation. In one embodiment, the present invention subjects the semiconductor substrate to an ashing environment. In the present embodiment, the ashing environment is comprised of H2O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas. In so doing, contaminants on the semiconductor substrate are removed. Next, the present invention subjects a mask covering a polysilicon stack to a mask-removal ashing environment. In the present embodiment, the mask-removal ashing environment is comprised of an O2 plasma. In so doing, the mask covering the polysilicon stack is removed. As a result, the semiconductor substrate and the top surface of the polysilicon stack are prepared for subsequent silicide formation thereon.

Abstract: A circuit monitor performance of an integrated circuit. The circuit includes a clock signal and a phase delay detection circuit. The clock signal is used by the integrated circuit to generate an output signal on an output pin of the integrated circuit. The phase delay detection circuit detects relative phase difference between the clock signal and the output signal on the output pin of the integrated circuit. The phase delay detection circuit includes a digital signal generator and an integrator. The digital signal generator is connected to an output pin of the integrated circuit. The digital signal generator generates a digital signal. Changes in phase delay between the output signal on the output pin of the integrated circuit and the clock signal used by the integrated circuit are encoded in a duty cycle of the digital signal generated by the digital signal generator. The integrator is connected to the digital signal generator and integrates the digital signal to produce an integrated signal.

Abstract: The present invention comprises a smart debug interface circuit for the diagnostic testing and debugging of a software application for a programmable digital processor system. The smart debug interface circuit of the present invention includes an instruction register for coupling to an instruction bus of a programmable digital processor. The instruction register is adapted to drive instructions onto the instruction bus. The instruction register couples to the instruction bus in a parallel manner. The smart debug interface circuit of the present invention includes a data register for coupling to a data bus of the programmable digital processor. The data register is adapted to read data from the data bus and couples to the data bus in a parallel manner. The instruction register and data register are each coupled to an interface port. The interface port couples the smart debug interface circuit to a host computer system.

Abstract: A CMOS wave shaping buffer circuit comprises two CMOS inverter stages connected as a non-inverting buffer. In addition, the two stages are further coupled by way of their supply connections to produce a positive feedback from the second stage to the first whenever both stages are driven to a linear state, that is both transistors of each stage are “ON”. The positive feedback prevents the output stage from remaining in a logically ambiguous state, but forces crisp transitions from one state to another even for slowly changing input signals.