Abstract: A computer array 100 including a field of processors 101-124 each processor having a separate memory. The processors 101-124 are connected to their immediate neighbors with links 200. Several configurations of the links are described including differing types of data lines 210 and control lines 215. Along lines 215 Process Command Words (PCW) to initiate processing tasks and Routing Connection Words (RCW) to initiate routing tasks pass between the processors 101-124 to provide a method for altering the mode of hybrid processors 107-118 in the array.

Abstract: A method and apparatus for dynamic partial reconfiguration on an array of processors. The method includes the steps of verifying if a processor is ready for dynamic partial reconfiguration to begin, deciding the degree of dynamic partial reconfiguration, including the number and identity of all processors to be modified, executing native machine code in the port of a processing device, and modifying a segment of the internal memory of said single processing device. Additional embodiments allow modification of multiple processors in the array, including the modification of all processors on a die or system.

Abstract: A novel memory circuit includes a pulse line, a memory latch including an enable port, and a pulse delay element interposed between the pulse line and the enable port of the memory latch. In a particular embodiment, the pulse delay element includes a series of logic gates. In a more particular embodiment, the series of logic gates include a feedback line for disconnecting the enable port from the pulse line. In another particular embodiment, the enable ports of two different memory latches are connected to the same pulse line via two different latch pulse delay elements, each having different delay times. In a more particular embodiment, the data output port of the first latch is connected to the data input port of the second latch.

Abstract: A system for performing parallel multiplication on a plurality of factors. In a binary processor, a first and a second memory have pluralities of bit-positions. The first memory holds a first value as a multiplier that will commonly serve as multiple of the factors, and the second memory holds a second value that is representative of multiple multiplicands that are other of the factors. A multiplier bit-count is determined of the significant bits in the multiplier. And a +* operation is performed with the first value and said second value a quantity of times equaling the multiplier bit-count.

Abstract: The apparatus described is a multi-core processor 505 adapted to provide digital to analog conversion. At least one 2010 of the cores 510 is used to make the conversion, another group of cores 2005 can provide the source of a digital stream of information such as audio visual signals. The stream is conveyed to processor 2010 optionally by a transfer processor 2015. The method of the invention divides each word of an incoming digital stream of information into a most significant and least significant portions. The most and least significant portions control the production of electrical charges which are added together to produce an analog electrical signal proportional to the values of the words in the digital stream.

Abstract: A sequential multiplier for multiplying a binary multiplier and a binary multiplicand to produce a final product. A first logic circuit generates a control signal based on the multiplier. A second logic circuit generates a partial product based on the control signal and the multiplicand. A full adder generates a partial sum and a partial carry in each of a sequence of cycles. In the first cycle the partial sum and the partial carry are both initialized to zero. In each said cycle the partial sum, the partial carry, and the partial product are added to generate a new partial sum and a new partial carry. After a last cycle, the partial sum is the final product.

Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The sleeping computer (12) can be awaiting data or instructions (12). In the case of instructions, the sleeping computer (12) can be waiting to store the instructions or to immediately execute the instructions. In the later case, the instructions are placed in an instruction register (30a) when they are received and executed therefrom, without first placing the instructions first into memory. The instructions can include a micro-loop (100) which is capable of performing a series of operations repeatedly.

Abstract: A method and apparatus for correlation of a received DSSS signal with a PN sequence, thus significantly reducing the processing time and operating power needed to acquire phase information for DSSS de-spreading and demodulation. The apparatus utilizes a multiprocessor array 10. In one embodiment, multiple processors 15 are located on a single-die 25, connected by single drop busses 20 to form low-operating-power apparatus. The method provides for fast sequential correlation of a received digital signal. In an alternate embodiment, the present invention is a single-die, low-operating-power apparatus and method for fast parallel correlation of a received digital signal. In yet another alternate embodiment, the present invention is a single-die, low-operating-power apparatus and method for fast correlation of a received digital signal using a hybrid of parallel and sequential methods.

Abstract: An integrated circuit simulator and method of integrated circuit simulation comprising providing a voltage lookup table having predetermined drain voltage data for a given transistor type, providing a voltage lookup table having predetermined gate voltage data for a given transistor type and providing a temperature lookup table having predetermined temperature data. Then simulating operation for each transistor in the integrated circuit by determining a current value through the transistor in dependence upon one of the predetermined voltage data values and one of the predetermined temperature data values; and simulating operation for each transistor in the integrated circuit by determining a transistor temperature value and incrementing a simulation time step and repeating the last two steps until simulations complete.

Abstract: A priority encoder and a processing device having the priority encoder. The priority encoder includes a port selector for generating a plurality of prioritized read requests based on a plurality of write requests from a plurality of processing devices and a predetermined priority assigned to each of the plurality of processing devices, one of the plurality of processing devices being selected based on the plurality of prioritized read requests; and a port latch for holding the values of the prioritized read requests to enable one of a plurality of communication ports unless the prioritized read requests are changed, each communication port for communicating with one of the processing devices to read data from the processing device.

Abstract: A zoned lighting space (10) wherein an architectural space is divided in to a plurality of zones (16), each having its own sensor(s) and zone lights (18). The zone lights (18) are controlled by a controller (20) such that there are different lighting levels (55, 57, 59) depending upon whether a zone (16) is occupied, whether an adjacent zone (16) is occupied, whether some other zone (16) is occupied, and the like. A variable lighting control method (50) is adaptable such that fine control and adaptation for special circumstances can be achieved.

Abstract: An integrated circuit simulator and method of integrated circuit simulation comprising providing a voltage lookup table having predetermined drain voltage data for a given transistor type, providing a voltage lookup table having predetermined gate voltage data for a given transistor type and providing a temperature lookup table having predetermined temperature data. Then simulating operation for each transistor in the integrated circuit by determining a current value through the transistor in dependence upon one of the predetermined voltage data values and one of the predetermined temperature data values; and simulating operation for each transistor in the integrated circuit by determining a transistor temperature value and incrementing a simulation time step and repeating the last two steps until simulations complete.

Abstract: A method of preparing a circuit simulator, said method comprising initializing a normalized adjusted gate voltage value. Then performing the steps of determining a normalized adjusted gate voltage datum in dependence upon the initial normalized adjusted gate voltage value. Storing the normalized adjusted gate voltage datum at a memory address in a one-dimensional array based on the normalized adjusted gate voltage. Decrementing the normalized adjusted gate voltage value by a predetermined decrement amount. And verifying the decremented gate voltage value. Then repeating until a stop gate voltage value is reached.

Abstract: A zoned interactive control area (10) wherein an architectural space is divided into a plurality of zones (16), each having its own sensor(s) and zone lights (18). The zone lights (18) are controlled by a controller (20) such that there are different lighting levels (55, 57, 59) depending upon whether a zone (16) is occupied, whether an adjacent zone (16)is occupied, whether some other zone (16)is occupied, and the like. A variable control method (50) is adaptable such that fine control and adaptation for special circumstances can be achieved. Other types of devices can also be controlled according to the present inventive method and apparatus.

Abstract: A memory cell including a bit and bitnot sense lines as well as a random access memory (RAM) word line and a read only memory (ROM) word line. The memory cell particularly includes a static RAM (SRAM) bit cell and a ROM bit cell. The SRAM bit cell is coupled between the bit and bitnot sense lines, and is responsive to a signal on the RAM word line. The ROM bit cell is also coupled between the bit and bitnot sense lines, and is responsive to a signal on the ROM word line. The ROM bit cell includes first and second ROM pass transistors, a first node for permanently programming connection of the first ROM pass transistor to either a voltage line or a ground line, and a second node for permanently programming connection of the second ROM pass transistor to either the voltage line or the ground line.

Abstract: The invention provides a method for improving the functionality of the jump button associated with television, cable/satellite receiver, or any other multi-channel device controlling remote control. The apparatus provides a jump button with the ability to access a wide variety of channels in an intelligent manner. At present, the jump button has the functionality such that the jump to location associated with selecting the jump button is the previously viewed channel, regardless of how the current channel being viewed is selected. The invention disclosed herein is a method of performing jumps on a device like a remote control in a more useful manner.

Abstract: A ring oscillator comprises a control circuit for receiving a frequency-selection signal operative to select from at least two ring oscillator frequencies, said control circuit using said control signal to generate a first control signal and a second control signal; a primary chain of an odd number of serially connected NOT gates, said primary chain including a primary switching NOT gate responsive to the first control signal and operative to perform a logical NOT or an IGNORE function on a first oscillating input signal to generate a first output signal; and a secondary chain of serially connected NOT gates, said secondary chain logically parallel to at least said primary switching NOT gate, said secondary chain including a secondary switching NOT gate responsive to the second control signal and operative to perform a logical NOT or an IGNORE function on a second oscillating input signal to generate a second output signal.

Abstract: An apparatus and method for converting a source signal at a first rate to a re-sampled signal at a second rate using an array of processors. A decoder decomposes the source signal into left and right source values and sends an aperture signal to a coefficient control unit upon decomposition completion. A transfer unit controllably receives and passes the left and right source values on to a re-sampler. The coefficient control unit calculates a polyphase offset based on the aperture signal and a clock signal. A coefficient server selectively passes coefficients to the re-sampler based on the polyphase offset. And the re-sampler generates the re-sampled signal based on the left and right source values and the coefficients.

Abstract: A digital logic level shifter having three stages. An initial stage includes a conventional 4-terminal bridge-type inverter circuit. A middle stage includes a 5-terminal first logic reversing circuit that has two middle stage inputs that are not connected in common. And a final stage includes a 5-terminal second logic reversing circuit that has two final stage inputs that are not connected in common.

Abstract: A method of integrated circuit simulation comprising the steps of providing a voltage lookup table having predetermined drain voltage data for a given transistor type, providing a voltage lookup table having predetermined gate voltage data for a given transistor type. Providing a temperature lookup table having predetermined temperature data. Providing a transistor lookup table having predetermined current and temperature data. Simulating operation of an integrated circuit by, for each transistor in the integrated circuit, determining a current value through the transistor in dependence upon one of the predetermined voltage data values and one of the predetermined temperature data values; and comparing the current value calculated to the current value obtained previously; and updating active transistor list detecting a change in the current value. Then incrementing a simulation time step and repeating simulation steps for all transistors.