Patents Assigned to VNS Portfolio LLC
  • Patent number: 10565362
    Abstract: Method and apparatus for authentication of a user to a server that involves the user performing a requested act and that further involves relative movement between the user and a camera wherein fiducial marks are captured.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: February 18, 2020
    Assignee: VNS Portfolio LLC
    Inventors: Beau Robertson Parry, Yasodekshna Boddeti
  • Publication number: 20190174630
    Abstract: A component support fixture having a plurality of oversized compartments of the same size mounted on a top surface of an anisotropic adhesive film such that each of a plurality of burned-in components of different heights and widths are accommodated within a compartment. Patterned traces are formed on the bottom surface of the anisotropic film. The leads of the burned-in components are in electrically communication with those traces through the anisotropic film.
    Type: Application
    Filed: February 5, 2018
    Publication date: June 6, 2019
    Applicant: VNS Portfolio LLC
    Inventor: Joseph Charles Fjelstad
  • Publication number: 20180307823
    Abstract: Method and apparatus for authentication of a user to a server that involves the user performing a requested act and that further involves relative movement between the user and a camera wherein fiducial marks are captured.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 25, 2018
    Applicant: VNS Portfolio LLC
    Inventors: Beau Robertson Parry, Yasodekshna Boddeti
  • Patent number: 10049203
    Abstract: Method and apparatus for authentication of a user to a server that involves the user performing a requested act and that further involves relative movement between the user and a camera wherein fiducial marks are captured.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: August 14, 2018
    Assignee: VNS Portfolio LLC
    Inventors: Beau Robertson Parry, Yasodekshna Boddeti
  • Patent number: 8120938
    Abstract: A method and apparatus for connecting multiple cores to form a multi core processor. Each processor is connected to at least two other processors, each of which is a mirror image of the first processor. The processors are connected to form a two dimensional matrix connected by one drop busses.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: February 21, 2012
    Assignee: VNS Portfolio LLC
    Inventors: Charles H. Moore, Jeffrey Arthur Fox, John W. Rible
  • Patent number: 8122226
    Abstract: A method and apparatus for dynamic partial reconfiguration on an array of processors. The method includes the steps of verifying if a processor is ready for dynamic partial reconfiguration to begin, deciding the degree of dynamic partial reconfiguration, including the number and identity of all processors to be modified, executing native machine code in the port of a processing device, and modifying a segment of the internal memory of said single processing device. Additional embodiments allow modification of multiple processors in the array, including the modification of all processors on a die or system.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: February 21, 2012
    Assignee: VNS Portfolio LLC
    Inventor: Gibson D. Elliot
  • Patent number: 8098157
    Abstract: A zoned interactive control area (10) wherein an architectural space is divided in to a plurality of zones (16), each having its own sensor (22) and zone lights (18). In a normal operating mode (50) the sensors (22) are used to detect the presence of a person such that the zone lights (18) can be turned on and/or adjusted for light level. Each zone light (18) also has a light sensor (24) used, at least in part, for communication with the other zone lights (18), such that the light level can be adjusted not just in response to a presence in the respective zone (16) but also in response to presence in other zones (16). According to a security method (70) when the zone lights (18) are not in use for normal lighting (as when they are turned off) then if the sensors (22) detect the presence of an intruder the zone lights (18) flash to deter the intruder and also communicate the fact of the presence of the intruder to the other zone lights (18) via the light sensors (22).
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: January 17, 2012
    Assignee: VNS Portfolio LLC
    Inventors: F. Eric Saunders, Gregory V. Bailey, Nicholas A. Antonopoulos
  • Patent number: 7996454
    Abstract: A method and apparatus for performing complex mathematical calculations. The apparatus includes a multicore processor 10 where the cores 15 are connected 20 into a net with the processors on the periphery 15a primarily dedicated to input/output functions and distribution of tasks to the central processors 15b-h of the net. The central processors 15b-h perform calculations substantially simultaneously, far exceeding the speed of conventional processors. The method 100, which may be implemented by an instruction set to the processor nodes, informs the processor nodes how to divide the work and conduct the calculations. The method includes steps dividing the data into subsets 110 directing the subsets to predetermined nodes 115, performing the calculations 120 and outputting the results 125.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: August 9, 2011
    Assignee: VNS Portfolio LLC
    Inventors: Paul Michael Ebert, Leslie O. Snively, Chiakeng (Jack) Wu
  • Patent number: 7984266
    Abstract: A computer array (10) has a plurality of computers (12) for accomplishing a larger task that is divided into smaller tasks, each of the smaller tasks being assigned to one or more of the computers (12). Each of the computers (12) may be configured for specific functions and individual input/output circuits (26) associated with exterior computers (12) are specifically adapted for particular input/output functions. An example of 25 computers (12) arranged in the computer array (10) has a centralized computational core (34) with the computers (12) nearer the edge of the die (14) being configured for input and/or output.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: July 19, 2011
    Assignee: VNS Portfolio LLC
    Inventor: Charles H. Moore
  • Patent number: 7971032
    Abstract: A process, apparatus, and system to execute a program in an array of processor nodes that include an agent node and an executor node. A virtual program of tokens of different types represents the program and is provided in a memory. The types include a run type that includes native code instructions of the executer node. A token is loaded from the memory and executed in the agent node based on its type. In particular, if the token is an optional stop type execution ends and if the token is a run type the native code instructions in the token are sent to the executor node. The native code instructions are executed in the executor node as received from the agent node. And such loading and execution continues in this manner indefinitely or until a stop type token is executed.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: June 28, 2011
    Assignee: VNS Portfolio LLC
    Inventor: Charles W. Shattuck
  • Patent number: 7966481
    Abstract: A microprocessor system in which an array of processors communicates more efficiently through the use of a worker mode function. Processors that are not currently executing code remain in an inactive but alert state until a task is sent to them by an adjacent processor. Processors can also be programmed to temporarily suspend a task to check for incoming tasks or messages.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: June 21, 2011
    Assignee: VNS Portfolio LLC
    Inventors: Charles H. Moore, Jeffrey Arthur Fox, John W. Rible
  • Patent number: 7937557
    Abstract: A computer array (10) has a plurality of computers (12) for accomplishing a larger task that is divided into smaller tasks, each of the smaller tasks being assigned to one or more of the computers (12). Each of the computers (12) may be configured for specific functions and individual input/output circuits (26) associated with exterior computers (12) are specifically adapted for particular input/output functions. An example of 25 computers (12) arranged in the computer array (10) has a centralized computational core (34) with the computers (12) nearer the edge of the die (14) being configured for input and/or output.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: May 3, 2011
    Assignee: VNS Portfolio LLC
    Inventor: Charles H. Moore
  • Patent number: 7934075
    Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously and operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The instructions executed by the computers (12) can include a micro-loop (100) which is capable of performing a series of operations repeatedly. In one application, the sleeping computer (12) is awakened by an input such that it commences an action that would otherwise required an interrupt of an otherwise active computer. For example, one computer (12f) can be used to monitor an input/output port of the computer array (10).
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: April 26, 2011
    Assignee: VNS Portfolio LLC
    Inventors: Charles H. Moore, Jeffrey Arthur Fox, John W. Rible
  • Patent number: 7913069
    Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. Instruction words (48) can include a micro-loop (100) which is capable of performing a series of operations repeatedly. In a particular example, the series of operations are included in a single instruction word (48). The micro-loop (100) in combination with the ability of the computers (12) to send instruction words (48) to a neighboring computer (12) provides a powerful tool for allowing a computer (12) to utilize the resources of a neighboring computer (12).
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: March 22, 2011
    Assignee: VNS Portfolio LLC
    Inventors: Charles H. Moore, Jeffrey Arthur Fox, John W. Rible
  • Patent number: 7904695
    Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. A slot sequencer (42) in each of the computers produces a timing pulse to cause the computer (12) to execute a next instruction. However, when the present instruction is a read or write type instruction, the slot sequencer does not produce the pulse until an acknowledge signal (86) starts it. The acknowledge signal (86) is produced when it is recognized that the communication has been completed by the other computer (12).
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: March 8, 2011
    Assignee: VNS Portfolio LLC
    Inventor: Charles H. Moore
  • Patent number: 7904615
    Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. A plurality of read lines (18), write lines (20) and data lines (22) interconnect the computers (12). When one computer (12) sets a read line (18) high and the other computer sets a corresponding write line (20) then data is transferred on the data lines (22). When both the read line (18) and corresponding write line (20) go low this allows both communicating computers (12) to know that the communication is completed. An acknowledge line (72) goes high to restart the computers (12).
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: March 8, 2011
    Assignee: VNS Portfolio LLC
    Inventor: Charles H. Moore
  • Publication number: 20110013467
    Abstract: A novel memory reading circuit includes a bit line for transmitting data bits within the memory, a plurality of storage elements for storing bits of data, and a precharge circuit coupled to the bit line for charging the bit line when the precharge circuit is in a charging state, the precharge circuit being operative to remain in the charging state at time when the storage elements assert the stored bits of data on the bit line. The memory may be a single-ended, static random access memory (“SRAM”). The SRAM circuits of the invention may be incorporated into each of a plurality of individual computers arrayed on a single die.
    Type: Application
    Filed: July 14, 2009
    Publication date: January 20, 2011
    Applicant: VNS PORTFOLIO LLC
    Inventor: Charles H. Moore
  • Patent number: 7840826
    Abstract: A computer array 100 including a field of processors 101-124 each processor having a separate memory. The processors 101-124 are connected to their immediate neighbors with links 200. Several configurations of the links are described including differing types of data lines 210 and control lines 215. Along lines 215 Process Command Words (PCW) to initiate processing tasks and Routing Connection Words (RCW) to initiate routing tasks pass between the processors 101-124 to provide a method for altering the mode of hybrid processors 107-118 in the array.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: November 23, 2010
    Assignee: VNS Portfolio LLC
    Inventor: Lonnie C. Goff
  • Publication number: 20100268911
    Abstract: A method and apparatus for dynamic partial reconfiguration on an array of processors. The method includes the steps of verifying if a processor is ready for dynamic partial reconfiguration to begin, deciding the degree of dynamic partial reconfiguration, including the number and identity of all processors to be modified, executing native machine code in the port of a processing device, and modifying a segment of the internal memory of said single processing device. Additional embodiments allow modification of multiple processors in the array, including the modification of all processors on a die or system.
    Type: Application
    Filed: April 16, 2009
    Publication date: October 21, 2010
    Applicant: VNS PORTFOLIO LLC
    Inventor: Gibson D. Elliot
  • Publication number: 20100254197
    Abstract: A novel memory circuit includes a pulse line, a memory latch including an enable port, and a pulse delay element interposed between the pulse line and the enable port of the memory latch. In a particular embodiment, the pulse delay element includes a series of logic gates. In a more particular embodiment, the series of logic gates include a feedback line for disconnecting the enable port from the pulse line. In another particular embodiment, the enable ports of two different memory latches are connected to the same pulse line via two different latch pulse delay elements, each having different delay times. In a more particular embodiment, the data output port of the first latch is connected to the data input port of the second latch.
    Type: Application
    Filed: April 1, 2009
    Publication date: October 7, 2010
    Applicant: VNS PORTFOLIO LLC
    Inventor: Charles H. Moore