Abstract: Method and apparatus for authentication of a user to a server that involves the user performing a requested act and that further involves relative movement between the user and a camera wherein fiducial marks are captured.

Abstract: Method and apparatus for authentication of a user to a server that involves the user performing a requested act and that further involves relative movement between the user and a camera wherein fiducial marks are captured.

Abstract: Method and apparatus for authentication of a user to a server that involves the user performing a requested act and that further involves relative movement between the user and a camera wherein fiducial marks are captured.

Abstract: Method and apparatus for authentication of a user to a server that involves the user performing a requested act and that further involves relative movement between the user and a camera wherein fiducial marks are captured.

Abstract: A component support fixture having a plurality of oversized compartments of the same size mounted on a top surface of an anisotropic adhesive film such that each of a plurality of burned-in components of different heights and widths are accommodated within a compartment. Patterned traces are formed on the bottom surface of the anisotropic film. The leads of the burned-in components are in electrically communication with those traces through the anisotropic film.

Abstract: Method and apparatus for authentication of a user to a server that involves the user performing a requested act and that further involves relative movement between the user and a camera wherein fiducial marks are captured.

Abstract: Method and apparatus for authentication of a user to a server that involves the user performing a requested act and that further involves relative movement between the user and a camera wherein fiducial marks are captured.

Abstract: A method and apparatus for dynamic partial reconfiguration on an array of processors. The method includes the steps of verifying if a processor is ready for dynamic partial reconfiguration to begin, deciding the degree of dynamic partial reconfiguration, including the number and identity of all processors to be modified, executing native machine code in the port of a processing device, and modifying a segment of the internal memory of said single processing device. Additional embodiments allow modification of multiple processors in the array, including the modification of all processors on a die or system.

Abstract: A method and apparatus for connecting multiple cores to form a multi core processor. Each processor is connected to at least two other processors, each of which is a mirror image of the first processor. The processors are connected to form a two dimensional matrix connected by one drop busses.

Abstract: A zoned interactive control area (10) wherein an architectural space is divided in to a plurality of zones (16), each having its own sensor (22) and zone lights (18). In a normal operating mode (50) the sensors (22) are used to detect the presence of a person such that the zone lights (18) can be turned on and/or adjusted for light level. Each zone light (18) also has a light sensor (24) used, at least in part, for communication with the other zone lights (18), such that the light level can be adjusted not just in response to a presence in the respective zone (16) but also in response to presence in other zones (16). According to a security method (70) when the zone lights (18) are not in use for normal lighting (as when they are turned off) then if the sensors (22) detect the presence of an intruder the zone lights (18) flash to deter the intruder and also communicate the fact of the presence of the intruder to the other zone lights (18) via the light sensors (22).

Abstract: A method and apparatus for performing complex mathematical calculations. The apparatus includes a multicore processor 10 where the cores 15 are connected 20 into a net with the processors on the periphery 15a primarily dedicated to input/output functions and distribution of tasks to the central processors 15b-h of the net. The central processors 15b-h perform calculations substantially simultaneously, far exceeding the speed of conventional processors. The method 100, which may be implemented by an instruction set to the processor nodes, informs the processor nodes how to divide the work and conduct the calculations. The method includes steps dividing the data into subsets 110 directing the subsets to predetermined nodes 115, performing the calculations 120 and outputting the results 125.

Abstract: A computer array (10) has a plurality of computers (12) for accomplishing a larger task that is divided into smaller tasks, each of the smaller tasks being assigned to one or more of the computers (12). Each of the computers (12) may be configured for specific functions and individual input/output circuits (26) associated with exterior computers (12) are specifically adapted for particular input/output functions. An example of 25 computers (12) arranged in the computer array (10) has a centralized computational core (34) with the computers (12) nearer the edge of the die (14) being configured for input and/or output.

Abstract: A process, apparatus, and system to execute a program in an array of processor nodes that include an agent node and an executor node. A virtual program of tokens of different types represents the program and is provided in a memory. The types include a run type that includes native code instructions of the executer node. A token is loaded from the memory and executed in the agent node based on its type. In particular, if the token is an optional stop type execution ends and if the token is a run type the native code instructions in the token are sent to the executor node. The native code instructions are executed in the executor node as received from the agent node. And such loading and execution continues in this manner indefinitely or until a stop type token is executed.

Abstract: A microprocessor system in which an array of processors communicates more efficiently through the use of a worker mode function. Processors that are not currently executing code remain in an inactive but alert state until a task is sent to them by an adjacent processor. Processors can also be programmed to temporarily suspend a task to check for incoming tasks or messages.

Abstract: A computer array (10) has a plurality of computers (12) for accomplishing a larger task that is divided into smaller tasks, each of the smaller tasks being assigned to one or more of the computers (12). Each of the computers (12) may be configured for specific functions and individual input/output circuits (26) associated with exterior computers (12) are specifically adapted for particular input/output functions. An example of 25 computers (12) arranged in the computer array (10) has a centralized computational core (34) with the computers (12) nearer the edge of the die (14) being configured for input and/or output.

Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously and operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The instructions executed by the computers (12) can include a micro-loop (100) which is capable of performing a series of operations repeatedly. In one application, the sleeping computer (12) is awakened by an input such that it commences an action that would otherwise required an interrupt of an otherwise active computer. For example, one computer (12f) can be used to monitor an input/output port of the computer array (10).

Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. Instruction words (48) can include a micro-loop (100) which is capable of performing a series of operations repeatedly. In a particular example, the series of operations are included in a single instruction word (48). The micro-loop (100) in combination with the ability of the computers (12) to send instruction words (48) to a neighboring computer (12) provides a powerful tool for allowing a computer (12) to utilize the resources of a neighboring computer (12).

Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. A plurality of read lines (18), write lines (20) and data lines (22) interconnect the computers (12). When one computer (12) sets a read line (18) high and the other computer sets a corresponding write line (20) then data is transferred on the data lines (22). When both the read line (18) and corresponding write line (20) go low this allows both communicating computers (12) to know that the communication is completed. An acknowledge line (72) goes high to restart the computers (12).

Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. A slot sequencer (42) in each of the computers produces a timing pulse to cause the computer (12) to execute a next instruction. However, when the present instruction is a read or write type instruction, the slot sequencer does not produce the pulse until an acknowledge signal (86) starts it. The acknowledge signal (86) is produced when it is recognized that the communication has been completed by the other computer (12).

Abstract: A novel memory reading circuit includes a bit line for transmitting data bits within the memory, a plurality of storage elements for storing bits of data, and a precharge circuit coupled to the bit line for charging the bit line when the precharge circuit is in a charging state, the precharge circuit being operative to remain in the charging state at time when the storage elements assert the stored bits of data on the bit line. The memory may be a single-ended, static random access memory (“SRAM”). The SRAM circuits of the invention may be incorporated into each of a plurality of individual computers arrayed on a single die.