Abstract: A digital logic level shifter having three stages. An initial stage includes a conventional 4-terminal bridge-type inverter circuit. A middle stage includes a 5-terminal first logic reversing circuit that has two middle stage inputs that are not connected in common. And a final stage includes a 5-terminal second logic reversing circuit that has two final stage inputs that are not connected in common.

Abstract: A method of integrated circuit simulation comprising the steps of providing a voltage lookup table having predetermined drain voltage data for a given transistor type, providing a voltage lookup table having predetermined gate voltage data for a given transistor type. Providing a temperature lookup table having predetermined temperature data. Providing a transistor lookup table having predetermined current and temperature data. Simulating operation of an integrated circuit by, for each transistor in the integrated circuit, determining a current value through the transistor in dependence upon one of the predetermined voltage data values and one of the predetermined temperature data values; and comparing the current value calculated to the current value obtained previously; and updating active transistor list detecting a change in the current value. Then incrementing a simulation time step and repeating simulation steps for all transistors.

Abstract: A method and apparatus for reducing latency in computer processors. The method incorporates a special instruction set that provides an indication of whether a particular instruction is capable of being executed nearly simultaneously with a preceding instruction in the same group. In such a situation, multiple instructions may be executed at a rate faster than expected. A simple apparatus for accomplishing this method is illustrated.

Abstract: The invention provides a method and apparatus for eliminating the stack overflow and underflow in a dual stack computer 100 while remaining fully operational in case of single event upset caused by radiation and a method and apparatus for eliminating stack overflow and underflow by replacing a conventional stack with a circular stack array 125B coupled to a plurality of multiplexers 205a-h to function in a circular repeating pattern. The method of the invention provides for the stack to remain operational in the event of single event upset by using one hot logic multiplexers 205a-h. Thus in case of single event upset, where the logic state of the control signals can be corrupted such that at a given time both the push or pop control signals are active, the multiplexers will not shift the data either upward or downward in the data stack 145 and the return stack 120 and prevents the processor system 100 from entering into an unknown state.

Abstract: A method and apparatus to gain additional functionality of a microprocessor by adding an extended instruction set mode. In this mode, the result of executing an instruction may be changed without changing the instruction itself. In the extended instruction set mode, there is an increase to the number of bits of precision when executing the plus instruction. An additional bit position is added to the program counter register. When this bit is set, the microprocessor is in extended instruction set mode. In addition, a new one bit latch is provided. The latch may be changed only when the microprocessor is in extended instruction set mode. The latch is defined as holding a true carry bit. A significant bit of a register holding a sum is saved in the carry latch at the end of the plus instruction.

Abstract: A method and apparatus for processing a stream of data. The apparatus includes an array of processors connected to one another by single drop busses. The data stream is inputed to one of the processors 305(da), which splits off a substream and passes the data stream onto a second processor 305(db), which repeats the process; this continues until all of the data stream has been split into substreams. Each substream is processed in parallel by a second grouping 315 of processors. This second group of processors may have multiple steps and processors 315, 320. The processed substreams are assembled into a single data stream 330 by a third group of processors 325 reversing the splitting process and outputted from the array by a last processor 305(ae).

Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The sleeping computer (12) can be awaiting data or instructions (12). In the case of instructions, the sleeping computer (12) can be waiting to store the instructions or to immediately execute the instructions. In the later case, the instructions are placed in an instruction register (30a) when they are received and executed therefrom, without first placing the instructions first into memory.

Abstract: A stack processor comprises a data stack with a T register, an S register, and eight hardwired bottom registers which function in a circular repeating pattern. The stack processor also comprises a return stack containing an R register, and eight hardwired bottom registers which function in a circular repeating pattern. The circular register arrays described herein eliminate overflow and underflow stack conditions.

Abstract: A method and apparatus for forming computer memory 10 including RAM, ROM, Stacks and other registers. The memory array 10 includes a number of individual memory cells 40, 42, 44, 46 connected to each other by word lines 18, 20 and bit lines 30, 32. Memory cells 40, 42, 44, 46 word lines 18, 20 and bit lines 30, 32 are oriented in a manner to provide minimum line length and a substantialy square geometry. The method includes arranging the memory cells in an interleaved formation.

Abstract: A method and apparatus for serialization of a transmitted data stream and deserialization of data on a single die chip 105, including a plurality of processors 110 on a single chip 105. The processors on the chip 105 are connected by single drop busses 120 and act as individual processors with at least some dedicated memory 118. The method of serializing includes initialization of a register serializing a most significant bit from said register, moving all bits in the direction of the most significant bit, replacing the least significant bit with a value of zero, and continuing said serializing and moving steps are continued until a stopping condition is met. The method of deserialization of a data word includes initializing a register used for deserialization, deserializing a bit, positioning the bit in the least significant bit of the register, moving all bits in the direction of the most significant bit, and continuing the positioning and moving steps until a stopping condition is reached.

Abstract: The method includes predetermining an output enable time period by measuring the maximum settling time when a signal is read during a transition from 0 to 1 or vice versa, and multiplying the maximum settling time by a safety factor 2.5, to set an output enable time period; reading and latching an input value; and transmitting the latched value onward after the predetermined output enable time period. An embodiment of the apparatus 10 includes two inverters 12, 14 and two pass gates 16, 18 and connected to a line 20 at its input. The pass gates 16, 18 are connected in a multiplexer configuration. A third pass gate 30 for connecting line 32, carrying the (inverted) output B of the metalatch, to further circuit portions, according to a 2-bit output enable signal applied to control lines 34, 36 respectively. In alternate embodiments, other logic circuit portions already provided can perform the function of pass gate 30.

Abstract: Disclosed is a system and method of adding functionality to a microprocessor, especially a RISC machine having a plurality of cores, with minimal changes in circuitry and while maintaining legacy features. An enhancement to the microprocessor involves modifying a program counter register (P-register). This invention increases the number of bits in the P-register from 9 to 10. A tenth bit signals an extended instruction mode. When the tenth bit is not set, microprocessor instructions perform legacy functions. When the tenth bit is set, the extended instruction mode is active and instructions perform different or enhanced functions.

Abstract: An improvement in sampling a high frequency input analog signal and converting it to a digital output signal is disclosed. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using multiple ADCs for multiple samplings, wherein each sampling is sequentially offset a fixed amount of time from the most recent preceding sampling. Each ADC has a designated central processing unit (CPU) to obtain sufficient data transfer capabilities. The samplings from the multitude of ADCs are a series of sequential digital output values.

Abstract: A novel a method for determining the internal operation of an integrated circuit (IC) includes measuring electromagnetic (EM) emissions from the integrated circuit chip and analyzing the EM emissions. In a particular method, the EM emissions from the IC are measured using an RF close end probe. In a particular method, the electromagnetic emissions are measured with the IC configured in various ways. In the normal operating mode, the emissions are measured while the IC is provided with power and any external clock signal(s). After measuring the emissions of the IC in normal operating mode, the IC is reconfigured by disabling the external clock signal(s) to the IC and remeasuring the emissions. The external clock signal is disabled by disconnecting the power to the IC, disabling the external clock signal, and then reconnecting power to the IC. In yet a third test mode, the external clock signal is reenabled while power continues to be supplied to the IC.

Abstract: A computer (12) having multiple data paths (38a-d) connecting to other devices, which may be similar computers. A register (40d) is provided that has bits (110) programmatically settable to address each of the data paths such that the computer can communicate via multiple of the data paths based on which bits are concurrently set in the register. The bits respectively represent instances of the other devices as source devices that the computer can read data from and instances of the other devices as destination devices that the computer can write data to. A single address in the register can represent both a source device and a destination device for data communicated by the computer. Optionally, multiple of the computers can be connected in series (termed a pipeline) or to form an array (10).

Abstract: A process, apparatus, and system to execute a program in an array of processor nodes that include an agent node and an executor node. A virtual program of tokens of different types represents the program and is provided in a memory. The types include a run type that includes native code instructions of the executer node. A token is loaded from the memory and executed in the agent node based on its type. In particular, if the token is an optional stop type execution ends and if the token is a run type the native code instructions in the token are sent to the executor node. The native code instructions are executed in the executor node as received from the agent node. And such loading and execution continues in this manner indefinitely or until a stop type token is executed.

Abstract: A method for converting analog values into digital form comprises comparing a current analog sample value with an analog input value to produce an outcome, generating a count value based on the outcome, the count value increasing upon successive like outcomes and being reset to an initial count value upon successive unlike outcomes, adding or subtracting the count value to/from a current digital sample value to generate a next digital sample value, the adding or subtracting being based on the outcome, and converting the next digital sample value to the current analog sample value.

Abstract: An improvement in sampling a high frequency input analog signal and converting it to a digital output signal is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using a different ADC for each sampling, wherein each sampling is sequentially offset a certain amount of time from the most recent preceding sampling. The samplings from the multitude of ADCs are combined to form a single contiguous digital output signal. Types of distributed sampling systems include a multitude of elongated trace patterns interconnected in series, a specified permittivity material device, and a sequencer or multiplier.

Abstract: The apparatus described is a multi-core processor 505 adapted to provide digital to analog conversion. At least one 2010 of the cores 510 is used to make the conversion, another group of cores 2005 can provide the source of a digital stream of information such as audio visual signals. The stream is conveyed to processor 2010 optionally by a transfer processor 2015. The method of the invention divides each word of an incoming digital stream of information into a most significant and least significant portions. The most and least significant portions control the production of electrical charges which are added together to produce an analog electrical signal proportional to the values of the words in the digital stream.