Abstract: The present disclosure generally relates to a dual free layer (DFL) two dimensional magnetic recording (TDMR) read head, and a method of forming thereof. The read head comprises a lower sensor, middle shields disposed on the lower sensor, and an upper sensor disposed on the middle shields. After the lower reader is formed, a dielectric layer is deposited around an outer perimeter of the lower shield. Portions of the dielectric layer are ion milled such that the remaining portions form a substantially flat layer. Another embodiment includes a deposition of a TaOx layer on the dielectric layer, where x is a numeral. Portions of the dielectric layer and the TaOx layer are then ion milled such that the remaining portions of the TaOx layer and the dielectric layer collectively form a substantially planar layer. The middle shields are formed over the lower reader and are substantially planar.

Abstract: Rather than waiting on a squelch to detect the difference in the state from steady to floating, this disclosure suggests using the time from when a reference clock is turned on to begin the process to exit the hibernation state. The reference clock is turned off while a data storage device is in the hibernation state to save power. Once the host is ready for the device to exit the hibernation state, the reference clock is turned on. The reference clock is monitored for the change. Once the reference clock is on, the data storage device returns to a steady state. In the ready state, the data storage device has a shortened ready time. Once the ready time is complete, the data storage device may now exit the hibernation state without waiting on squelch detection or a hibernation exit request from the host.

Abstract: The present disclosure generally relates to memory management during SGL fetching. When a data storage device is required to fetch an SGL from a host device, the data storage device cannot determine how much memory will be required to be allocated. The disclosure herein reduces the impact of the problem of under or over allocating memory and over-fetching, thereby reducing performance of the device during transfers. The disclosure provides guidance on how to implement an adaptive learning process based upon statistic collection of SGL fetches. By maintaining a table of statistics, the data storage device controller may learn and more closely predict an amount of memory to allocate for SGL fetching.

Abstract: A read to a wordline can cause a read disturb error on neighboring wordlines. Instead of scanning the entire memory to identify wordlines that have a read disturb problem, a localized read scan approach can be used. In this approach, the memory is organized into several zones, where each zone contains several wordlines. The number of reads in each zone is tracked, and, after a certain number of reads, the data in the zone is read. If the error rate of the data exceeds a threshold, the data is relocated to another area of the memory.

Abstract: Example systems, read channels, and methods provide an oversampled digital phase lock loop for use in a read channel. The phase lock loop receives a digital data signal comprised of oversampled digital signal values with a sample rate that is a multiple of the baud rate of the channel. A set of oversampled digital signal values is selected for each iteration of the phase lock loop to correct the phase of an analog-to-digital converter. The phase lock loop determines a phase gradient, based on an iterative detector, and feeds back a phase correction for the next iteration of the phase lock loop. A baud rate digital data signal is provided to the rest of the channel based on down sampling or interpolated based on the phase gradient.

Abstract: A data storage device includes a memory device including a plurality of wordlines, each wordline having a plurality of cells, and a cell statistics generator (CSG) disposed on the memory device. The CSG includes logic configured to receive a plurality of left read senses and a plurality of right read senses for the plurality of cells of a wordline, determine a plurality of first windows and a plurality of second windows, determine a left window sum and a right window sum, determine a deviation parameter and a dispersion parameter based on the left window sum and the right window sum, and determine one or more characteristics of the plurality of cells based on the deviation parameter and the dispersion parameter. The deviation parameter and the dispersion parameter are used to describe a number of errors of the left read sense and the right read sense.

Abstract: The present disclosure generally relates to a tape drive having a regenerative braking system. The tape drive comprises a first reel; a first spindle coupled to the first reel; a first motor coupled to the first spindle, wherein the first motor is configured to rotate the first spindle; a second reel; a second spindle coupled to the second reel; a second motor coupled to the second spindle, wherein the second motor is configured to rotate the second spindle; and a regenerative braking circuit coupled to the first motor and the second motor, wherein during a braking of the motors, the regenerative braking circuit and the motors convert a mechanical energy of the motors to electrical energy for a power storage mechanism, thereby providing resistance to the rotation of the spindles.

Abstract: This disclosure includes back pattern counter measures for solid state drives. Embodiments described herein include setting and applying read threshold offsets according to flags set based on an amount of data stored within a memory block (e.g., an “openness” of the block). The flag is implemented during read commands to account for shifts in voltage distribution of open blocks. A value of the flag may be chosen based on a number of word lines included in the block that store data. The read threshold offsets may further be based on at least one of the set flag or an age of a respective NAND cell.

Abstract: To remedy short term data retention issues, a non-volatile memory performs a multi-pass programming process to program data into a set of non-volatile memory cells and identifies non-volatile memory cells that experienced downward threshold voltage drift after a first pass of the multi-pass programming process and prior to a final pass of the multi-pass programming process. The final pass of the multi-pass programming process comprises programming non-volatile memory cells not identified to have experienced the downward threshold voltage drift to a set of final target threshold voltages and purposefully overprogramming non-volatile memory cells identified to have experienced the downward threshold voltage drift to threshold voltages greater than respective final target threshold voltages by one or more offsets.

Abstract: Disclosed are systems and methods for large write planning for performance consistency and resource usage efficiency. A method is implemented using one or more controllers for one or more storage devices. The method includes receiving, via a host interface, a notification of a write data burst. The method also includes computing available spaces in a plurality of memories and a write ratio, to handle the write data burst to the plurality of memories, based on the notification. The method also includes receiving, via the host interface, the write data burst. The method also includes, in response to receiving the write data burst, toggling writes between the plurality of memories, based on the available spaces and the write ratio.

Abstract: Disclosed are systems and methods detecting and isolating faulty hold-up capacitors and performing corrective actions for a data storage device. A hardware circuit is coupled to a micro-controller and non-volatile memory dies. The method includes, at the hardware circuit: providing a back-up power for the non-volatile memory dies and the micro-controller; and detecting whether a hold-up capacitor of the hardware circuit is faulty and isolating the hold-up capacitor in accordance with a detection that the hold-up capacitor is faulty. The method also includes, at the micro-controller: obtaining a status of an interface coupled to the hardware circuit; determining a status of the hardware circuit based on the status of the interface; and performing a corrective action for the data storage device in accordance with a determination that the status of hardware circuit corresponds to one or more faulty hold-up capacitors.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to add one or more entries to a log file system (LFS) invalidation table and scan the LFS invalidation table during a storage optimization operation. Each entry of the one or more entries maps a new valid logical block address (LBA) to an old invalidated LBA. The new valid LBA is updated version of the old invalidated LBA. The storage optimization operation includes moving data from a first location to a second location.

Abstract: A non-volatile storage system includes a memory controller and multiple integrated memory assemblies separate from and in communication with the memory controller. The integrated memory assemblies each comprises a memory die and a control die. The control die is connected (e.g., bonded) to the memory die. The memory controller and the control die include separate compute resources (e.g., each includes a processor). The storage system is configured to receive a request to perform a compute task and assign that compute task to any one or more of the memory controller and the integrated memory assemblies based on anticipated amount of data to be transferred to or from non-volatile memory for the compute task, computational resource need of the compute task, and/or available bandwidth of the memory controller and the control dies.

Abstract: The present disclosure generally relates to a flip chip assembly having a bump that reduces stress levels in a low-k dielectric layer in the flip chip. Rather than having a single, large area plateau that interfaces with a large corresponding opening of an insulating layer in the flip chip, the bump includes a plurality of much smaller pillars that interface with a corresponding plurality of openings in the insulating layer. In so doing, the low-k layer within the flip chip experiences much less stress and hence, fewer failures.

Abstract: A data storage device has a closed loop extended park mode during spin down operation. A data storage device comprises a spindle motor configured to rotate one or more disks, and one or more processing devices. The one or more processing devices are configured to determine a value of current that is discharged from the spindle motor over time during a spin down of the spindle motor, and control a braking duty cycle for braking the spindle motor during the spin down such that the value of current discharged from the spindle motor over time does not exceed a selected current limit.

Abstract: Disclosed herein are systems for detecting molecules. In some embodiments, a system includes a multiplexer, a read amplifier coupled to the multiplexer, a digitizer coupled to the read amplifier, a first nanopore, a first sense electrode situated on a first side of the first nanopore, a first counter electrode situated on a second side of the first nanopore, a first shield at least partially surrounding the first sense electrode and coupled to the multiplexer, a first shield driver coupled to the first shield, drive circuitry coupled to the first sense electrode, and control logic coupled to the drive circuitry, the multiplexer, and to the digitizer. In some embodiments, the control logic is configured to control the drive circuitry and/or the multiplexer to select the first sense electrode and/or the first counter electrode, and obtain a digitized signal from the digitizer, the digitized signal representing a current through the first nanopore.

Abstract: The present disclosure generally relates to improved address translation. Rather than fetching translated addresses using ATS/ATC, a HIM address translation search engine (HATS) is used through implementing the ATC in a layer above per an NVMe command. The HATS is an engine that will monitor pointers with untranslated addresses and will fetch the translated addresses for the pointers. Once the translated addresses are fetched for the pointer, the HATS will overwrite the untranslated address with the translated address. The HATS will then update the status of the pointers. When a translation request fails, the device will use PRI to request the translated address. During a translation request fail the device will drain any incoming requests while skipping the data transfer phase. The device will not block any other requests in a queue. Once that translated address is received through the PRI flow, the status of the pointer will be updated.

Abstract: The present disclosure is generally related to a magnetic recording device comprising a magnetic recording head. The magnetic recording head comprises a main pole, a shield, and a spintronic device disposed between the main pole and the shield. The spintronic device comprises two field generation layers (FGLs), two spin polarization layers (SPLs), and two spin kill layers. The spintronic device further comprises one or more optional thin negative beta material layers, such as layers comprising FeCr, disposed in contact with at least one of the spin kill layers. When electric current is applied, the spin kill layers and optional negative beta material layers eliminate or reduce any spin torque between the FGLs and the SPLs.

Abstract: The present disclosure generally relates to improved optimization of a cache lookup operation by structuring the write cache buffers differently using a link-list. Rather than executing a read command first and then executing a write command only after the read command is executed, this disclosure suggests reordering the command executions. A device waits before executing the read command giving the opportunity to obtain the overlap write command. The device then reorders the command execution and executes first the write command and then executes the read command by accessing the write cache instead of the NAND. When two write commands need to be executed consecutively, the link-list operation is used. The controller finds the relevant buffer in the cache that is needed and overwrites the buffer with the new data. The new data is then written to the cache without accessing the cache multiple times.

Abstract: The present disclosure generally relates to read and write operations utilizing barrier commands. Using barrier commands and a snapshot of doorbell states of submission queues (SQs), the necessary write commands to perform a read may be identified and executed to reduce any wait time of the host. As such, host delays during reads and writes are reduced. In absence of a barrier command, the host needs to wait for writes to complete before performing a read. When a barrier command is used, the host needs to wait for the barrier command to complete before performing a read. The controller will execute the post barrier reads only after completing the pre-barrier writes. As will be discussed herein, the controller completes the barrier command as soon as a doorbell snapshot is taken even though the pre-barrier writes may not yet be completed.