Abstract: The present disclosure generally relates to a magnetic recording head for a magnetic media drive. The magnetic recording head comprises a main pole, a waveguide disposed adjacent to the main pole, a thermal shunt disposed between the main pole and the waveguide, the thermal shunt being recessed from a media facing surface (MFS), and a near field transducer (NFT) coupled between the main pole and the waveguide at the MFS. The NFT comprises a first metal layer disposed adjacent to the waveguide and in contact with a first insulating layer, a dielectric gap layer disposed on and in contact with the first metal layer, and a second metal layer disposed on and in contact with the dielectric gap layer and a second insulating layer. The first metal layer, the dielectric gap layer, and the second metal layer are each disposed in contact with the thermal shunt.

Abstract: The present disclosure generally relates to a tape drive comprising a tape wound around first and second tape reels and a tape head module configured to write data to and read data from the tape. The tape drive is configured to equalize the amount of time the tape spends stored in a first state and a second state when being stored long term, or when in a preservation phase, to minimize the effects of creep and tape dimensional stability. In the first state, a majority of the tape is wound around the first tape reel. In the second state, the majority of the tape is wound around the second tape reel. The tape drive is configured to move the tape between the first and second states: (1) upon being triggered by the timer, or (2) based on the tape head module being utilized to determine a position error signal.

Abstract: Read commands and write commands are issued by a data storage device, but sometimes a read command can begin execution prior to the data for the write command having been written to the memory device (or HMB DRAM). In such a scenario, the data for the read command is not in the memory device, but rather, is in cache waiting to be written to the memory device in a write cache operation. In order to ensure the correct data is read, the cache write operation can be paused so that the data can be retrieved from cache rather than the memory device. Alternatively, a placeholder can be used for the read command until the write cache operation has occurred.

Abstract: Contents of the next commands are considered as part of an arbitration between virtual functions (VFs). The device controller will hold the head of the submission queues (SQ) internally. The controller is able to do so by implementing a small first in first out (FIFO) per submission queue. The second arbiter and the main arbiter, which is responsible for the command scheduling, fetches the commands from the internal small FIFO. Using this technique, the second arbiter gains visibility of the next commands that participate in the arbitration since the next commands are held internally and not in host memory.

Abstract: Instead of handling resources with one generic method, the controller can use a static method or dynamic method to handle the resources. The controller communicates to the host as to the number of resources the controller has for keeping doorbell times. The controller will also communicate with the host how those resources are used. The static method focuses on creating dedicated submission queues (SQ), while the dynamic method provides a hint during the doorbell execution. The static method further focuses on improving priority, while the dynamic method focuses on canceling commands that have timed out. The static method and the dynamic method can be combined to further support the hosts requirements.

Abstract: The present disclosure is generally related to a deep neural network (DNN) device comprising a plurality of spin-orbit torque (SOT) cells. The DNN device comprises an array comprising n rows and m columns of nodes, each row of nodes coupled to one of n first conductive lines, each column of nodes coupled to one of m second conductive lines, each node of the n rows and m columns of nodes comprising a plurality of SOT cells, each SOT cell comprising: at least one SOT layer, at least one ferromagnetic (FM) layer, and a controller configured to store at least one corresponding weight of an n×m array of weights of a neural network in each of the SOT cell. The FM layer may comprise two or more domains, two or more elliptical arms, or two or more states.

Abstract: Technology for determining a test flow for testing memory during a production phase. The following are accessed: a list of test items with a number of candidate test item conditions for each test item, defects (e.g., bad blocks) detected by each test item condition, a list of benchmark defects (e.g., bad blocks), and judgement criteria. The defects (e.g., bad blocks) for the candidate test item conditions may be compared with the benchmark defects (e.g., bad blocks) in view of judgement criteria. Based on the comparison, at least one test item may be eliminated resulting in a set of remaining test items. A production phase test flow having a test item condition for each remaining test item may be generated.

Abstract: Embodiments described herein aim to optimize the Erratic Program Detection (EPD) process by eliminating unnecessary operations and adjusting operations that are not optimized for the EPD process. For example, one optimization includes the EPD read operations being performed based on a read mode optimized for faster data retrieval. Further, another optimization includes a first read voltage ramping up at a rate that is faster than a ramp rate used to ramp up a read voltage during performance of a normal read operation. Another optimization also includes a read voltage kick operation between the EPD read operations being eliminated. Finally, another optimization includes parallelizing the scan operation with other ongoing operations.

Abstract: A data storage device has an inference engine that can infer a read threshold based on a non-linear function of inputs that reflect current memory and data conditions. The read threshold can be used in reading a wordline in the memory. Using a machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and also improve latency, throughput, power consumption, and quality of service.

Abstract: The present disclosure generally relates to a magnetic recording head for a magnetic media drive. The magnetic recording head comprises a main pole, a waveguide disposed adjacent to the main pole, a thermal shunt disposed between the main pole and the waveguide, the thermal shunt being recessed from a media facing surface (MFS), and a near field transducer (NFT) coupled between the main pole and the waveguide at the MFS. The NFT comprises a first metal layer disposed adjacent to the waveguide and in contact with a first insulating layer, a dielectric gap layer disposed on and in contact with the first metal layer, and a second metal layer disposed on and in contact with the dielectric gap layer and a second insulating layer. The first metal layer, the dielectric gap layer, and the second metal layer are each disposed in contact with the thermal shunt.

Abstract: The present disclosure generally relates to a dual free layer two dimensional magnetic recording read head. The read head comprises a lower shield, a first sensor disposed over the first lower shield, a first rear hard bias (RHB) structure recessed from a media facing surface (MFS), a first upper shield disposed over the first sensor, a middle shield disposed over the first sensor at the MFS, a second sensor disposed over the middle shield, a second RHB structure recessed from the MFS, and an upper shield disposed over the second sensor. The middle shield has a U-like shape and a ratio of a width to a throat height of 6:1, where the throat height is less than or equal to about 2 ?m. The first and second RHB structures each individually has a stripe height about 3 times greater than a stripe height of the middle shield.

Abstract: Various devices, such as storage devices or systems are configured to efficiently process and update logical mappings within control table sets. Control table sets are often groupings of logical mapping corresponding to the logical locations of data requested by a host-computing device and the physical locations of the data within the memory array. As data is written and erased, these mappings must be updated within the control table set. Received changes to these mappings are typically stored and updated in two locations: a cache memory and a control table update list. By tracking and marking various control table sets as dirty or having undergone multiple changes, additional received updates can be stored and updated in only the cache memory, bypassing the second control table change list. By only utilizing one method of updating control table sets, processing overhead is reduced and various read or write activities are more efficiently done.

Abstract: A two-dimensional magnetic recording (TDMR) read head includes a lower reader and an upper reader. Each of the lower reader and the upper reader may have a dual free layer (DFL) magnetic tunnel junction structure having first and second free layers located between lower and upper shields. A synthetic antiferromagnetic (SAF) structure is located on a side of each magnetic tunnel junction. A sidewall insulating layer is located between the lower soft bias layer of the SAF structure and the first free layer. The sidewall insulating layer can have a reduced height such that an upper soft bias layer of the SAF structure is in direct contact with a sidewall of the second free layer, or the upper portion of the sidewall insulating layer located between the upper soft bias layer of the SAF structure and the sidewall of the second free layer has a reduced thickness.

Abstract: A method of sensing molecules using a detection device, the detection device comprising a plurality of magnetoresistive (MR) sensors and at least one fluidic channel, comprising adding a plurality of molecules to be detected to the at least one fluidic channel, wherein at least some of the plurality of molecules to be detected are coupled to respective magnetic nanoparticles (MNPs), detecting a characteristic of a magnetic noise of a first MR sensor of the plurality of MR sensors, wherein the characteristic of the magnetic noise is influenced by a presence of one or more MNPs in a vicinity of the first MR sensor, and determining, based on the detected characteristic, whether the first MR sensor detected the presence of one or more MNPs in the vicinity of the first MR sensor.

Abstract: Technology for managing non-volatile memory. A bitmap may be maintained in NAND memory cells. The bits in the bitmap map to an address (e.g., PBA) in the NAND memory cells. Each bit has either a first value to indicate that the corresponding address stores valid data or a second value to indicate that the corresponding address does not store value data. Garbage collection may be performed based on the bitmap. Bit-level memory operations are performed to maintain the bitmap. Bit-level erase may be performed to erase a memory cell to have a value that indicates a valid/invalid status. The bitmap may contain unencoded data. In one aspect, a one's complement to the bitmap is stored in the NAND memory cells. The one's complement has opposite values as the regular bitmap. The system may compare the values in the regular bitmap and the one's complement bitmap for data integrity.

Abstract: A storage device may use unused bits in a memory device communicatively coupled to the storage device to reduce resource usage and time on the storage device during background operations. The memory device includes a plane having a redundant column section including unused bits. When the storage device receives instructions from a host device, a controller on the storage device may determine that the instructions are associated with data to be discarded from the memory device and may associate the data to be discarded with fragments in the memory device. The controller may generate relocation information, associate the relocation information with data stored in the memory device, and store the relocation information in the unused bits. During relocation operations, the controller may use the relocation information to determine whether fragments in the memory device include the data to be discarded and/or whether to move data in the memory device.

Abstract: Instead of entering lanes into an unused power state, enter unactive lanes into an unconnected power state to save more current during low power states. Using a small control logic will allow a controller to control unactive lanes in low power mode. When a lane is in an unactive power state or in an unused power state, an unactive lane controller (ULC) uses side-band signaling to place the unactive lane into either unused power state or unconnected power state. When a lane is in unused power state, then the ULC places the lane in unconnected power state. A single ULC is able to controller multiple lanes or you can have multiple ULC's, each controlling a single lane.

Abstract: A multi-protocol storage device avoids entering a thermal shutdown mode by switching between protocols. The storage device communicates with a host in a first mode using a first protocol. The storage device receives a temperature request from the host, monitors its temperature, and transmits a response to the host when the temperature of the storage device meets a predefined temperature that is below a thermal shutdown threshold. The storage device receives a thermal throttling instruction from the host and switches to a second mode to communicate with the host using a second protocol that uses less resources than the first protocol. The storage device performs thermal throttling until the temperature of the storage device reaches a normal temperature zone. When the temperature of the storage device returns to the normal temperature zone, the storage device returns to the first mode.

Abstract: A key-value storage device may perform error-handling on key-value data stored in a memory device. The key-value storage device may be communicatively coupled to a host device that may transmit read commands to retrieve the key-value data stored on the memory device. In response to a read command, the storage device may retrieve the key-value data from the memory device. If during retrieval the storage device identifies that a portion of the key-value data is irretrievable, the storage device may perform an error-handling operation on the key-value data. Depending on a key-value data type, the storage device may perform an error concealment operation and return complete key-value data or a partial error-handling operation and return partial key-value data to the host.

Abstract: A storage device maintains uniform write performance for data written to a memory device including varying block sizes. The storage device includes a balancing module to ensure that free blocks exist in a partition on the memory device and to define a garbage collection threshold based on blocks available in the partition. The storage device also includes a controller to receive host data from a host device, write the host data to the memory device; and relocate the host data in the memory device during a background operation. The controller initiates the background operation on the memory device at the garbage collection threshold and executes the background operation according to a host write-to-relocation write ratio based on a dynamically calculated size of the remaining free blocks in the partition.