Abstract: Disclosed are systems and methods for large write planning for performance consistency and resource usage efficiency. A method is implemented using one or more controllers for one or more storage devices. The method includes receiving, via a host interface, a notification of a write data burst. The method also includes computing available spaces in a plurality of memories and a write ratio, to handle the write data burst to the plurality of memories, based on the notification. The method also includes receiving, via the host interface, the write data burst. The method also includes, in response to receiving the write data burst, toggling writes between the plurality of memories, based on the available spaces and the write ratio.

Abstract: Technology is disclosed herein for early erase termination as a counter-measure for erase disturb. Multiple erase blocks of NAND memory cells are erased in parallel during an erase procedure. Erasing multiple erase blocks in parallel can place considerable strain on the circuitry that generates the erase voltage. If there is significant leakage current in one of the erase blocks the magnitude of the erase voltage for all of the erase blocks may drop. The erase blocks are tested sequentially for leakage current during the first erase loop while the erase voltage is applied to only the erase block under test. If any erase block fails the leakage current test that erase block is removed from the erase procedure. One or more additional erase loops are then performed with only those erase blocks that passed the leakage current test simultaneously receiving an erase voltage, thereby preventing erase disturb with early termination.

Abstract: Various processes for efficiently and effectively managing huge pages include a process for optimizing memory deduplication of huge pages, optimizing the promotion of one or more base pages to one or more huge pages and optimizing memory compaction of a memory space associated with a huge page.

Abstract: A data storage device and method for lane detection and configuration are provided. In one embodiment, a data storage device is provided comprising a memory, an interface, and a controller. The controller is configured to detect whether a cable coupled with the interface is providing a first channel configuration signal that indicates that the cable is in a first cable orientation or a second channel configuration signal that indicates that the cable is in a second cable orientation. In response to detecting that the cable is not providing either the first or the second channel configuration signal, the controller uses a default lane configuration to communicate with the host via the cable. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.

Abstract: Host data stream assignment with space-leveling across storage block containers. In one example, a data storage device including an electronic processor that, when executing a space-leveling scheme, is configured to receive a first host data stream, store the first host data stream in a block container assignment queue (BCAQ), detect a next storage block container switching event, responsive to detecting the next storage block container switching event, randomly select a location of the BCAQ, responsive to randomly selecting the location of the BCAQ, assign a second host data stream located at the location of the BCAQ that is selected to a storage block container of a memory, and control the memory to store the second host data stream in the storage block container that is assigned.

Abstract: Embodiments of the present disclosure generally relate to spintronic devices, and more specifically to self-cooling spintronic devices. In an embodiment, a device is provided. The device includes a spintronic device having a first side and a second side opposite the first side, a first layer disposed on the first side, and a second layer disposed on the second side, the first layer having a Seebeck coefficient that is different from a Seebeck coefficient of the second layer.

Abstract: A hard disk drive flexible printed circuit (FPC) includes a plurality of fingers extending from a main portion, with each finger having a first wiring layer including a first electrically conductive trace layout, a second wiring layer including a second electrically conductive trace layout, and a base film interposed between the first and second wiring layers, where the first conductive trace layout includes at least one thermally conductive protective island overlaying a respective portion of the second trace layout to provide a protective thermal barrier to the base film. Hence, maximum temperatures across various layers of the FPC laminate can be reduced, damage to the FPC prevented, and manufacturing yields improved.

Abstract: The devices, methods, and apparatuses of the present disclosure address a lack of parallelism in a typical approach by eliminating the static mapping of the two or more low-density parity check (LDPC) engines to a plurality of flash controllers. The devices, methods, and apparatuses of the present disclosure include a dynamic LDPC mapping to the plurality of flash controllers.

Abstract: A Zoned Namespace data storage device configured to perform logical-to-physical (L2P) address translation using a compacted L2P having an erase-block granularity. For a host logical address, the compacted L2P table only has the physical address of the corresponding erase block, which provides a first part of the pertinent physical address. A controller of the data storage device calculates a second part of the pertinent physical address based on the superblock layout employed in the device and further based on the sequential write requirement to the superblocks. The controller then obtains the full physical address corresponding to the host logical address by combining the first and second parts. The erase-block granularity of the compacted L2P table enables the full L2P table of the device to have a relatively small size, which can beneficially be used to make more space available in the same amount of RAM for other operations.

Abstract: The present disclosure generally relates to a dual free layer (DFL) read head and methods of forming thereof. In one embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a stripe height of the DFL sensor, depositing a rear bias (RB) adjacent to the DFL sensor, defining a track width of the DFL sensor and the RB, and depositing synthetic antiferromagnetic (SAF) soft bias (SB) side shields adjacent to the DFL sensor. In another embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a track width of the DFL sensor, depositing SAF SB side shields adjacent to the DFL sensor, defining a stripe height of the DFL sensor and the SAF SB side shield, depositing a RB adjacent to the DFL sensor and the SAF SB side shield, and defining a track width of the RB.

Abstract: A data storage disk cartridge library system includes a rack having an array of bays, at least some housing disk media cartridges and/or media drives, and a pair of horizontal and vertical guide rails bordering each bay. A media transport robot includes fixed-position drive wheels at each corner for driving the robot along the guide rails, and pivoting guide wheels corresponding to each drive wheel for guiding the drive wheel horizontally along a horizontal guide rail and vertically along a vertical guide rail. With each guide wheel coupled with a horizontal guide rail the robot can travel horizontally on the rack, and with each guide wheel coupled with a vertical guide rail the robot can travel vertically on the rack. Electrical power can be supplied to the robot via the guide rails, and gear portions of the wheels mechanically interface with a mechanical portion of the guide rails.

Abstract: Various illustrative aspects are directed to a data storage device, comprising one or more disks; an actuator mechanism configured to position heads proximate to a recording medium of the disks; a spindle motor configured for rotating the one or more disks; and one or more processing devices comprising a servo control processor. The servo control processor is configured to receive a spindle speed error signal indicative of an error in a rotational speed of the spindle motor. The servo control processor is further configured to output an initial frequency offset signal, wherein the initial frequency offset signal is proportional to the spindle speed error signal.

Abstract: Example storage systems, storage devices, and methods provide novel management of storage device compute operations using intermediate results, such as approximate or partial results, to optimize processing flow. An example system has a storage medium and a storage controller coupled to the storage medium that is configured to evaluate a processing capability of a storage device and determine, based on the processing capability, that only a portion of a multi-stage compute operation is completable within a requested processing timeframe. The storage processor may further be configured to determine and provide an intermediate result, which may include an approximation or a partial result of the multi-stage compute operation. The intermediate result may be used by a client to manage its own processing while it awaits a final processing result.

Abstract: Example storage systems, storage devices, and methods provide management of idle time compute tasks from host systems. Storage devices may receive host storage commands for reading and writing host data and host compute commands for executing host compute tasks. Some host compute commands may include a scheduling tag. The storage device may operate in a storage processing state and an idle state and may selectively execute delayed host compute tasks during the idle state.

Abstract: A non-volatile storage apparatus includes a plurality of non-volatile memory cells formed on a memory die, each non-volatile memory cell configured to hold a plurality of bits of data, and a control circuit formed on the memory die. The control circuit is configured to calculate parity data for data to be stored in the memory cells and program the memory cells to first distributions. The control circuit is also configured to read memory cells in the first distributions, recover the data from results of reading the memory cells in the first distributions combined with the parity data, and further program the memory cells from the first distributions to second distributions to store the data.

Abstract: Various illustrative aspects are directed to a data storage device, comprising one or more disks; an actuator mechanism configured to position one or more heads proximate to one or more disk surfaces of the one or more disks; and one or more processing devices, comprising an actuator mechanism control system configured for controlling the actuator mechanism. The one or more processing devices are configured to: output a multi-rate excitation to at least one multi-rate notch filter of the actuator mechanism control system; detect a frequency response of the actuator mechanism in response to the multi-rate excitation; and calibrate the at least one multi-rate notch filter of the actuator mechanism control system, based at least in part on the detected frequency response of the actuator mechanism.

Abstract: A surface mount device having features on contacts to prevent the surface mount device from tombstoning. The feature may be channel defined by the contact that helps balance a torque/force applied on each side of the surface mount device during a reflow soldering process. The feature may also be a solder mask that helps balance a torque/force applied on each side of the surface mount device during a reflow soldering process.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to compare a first copy of a boot partition to a second copy of the boot partition. The first copy of the boot partition and the second copy of the boot partition each comprises a same number of a plurality of boot chunks. The boot partition corresponds to data of a boot operation of a host device. The controller is further configured to mark one or more of the compared boot chunks that equals or exceeds a similarity threshold and update a reliability index based on the marking. Based on the marking and the reliability index, the controller may increase or decrease an amount of error correction needed for the boot data.

Abstract: An apparatus includes a first encoder circuit configured to compress a block of data using dictionary based compression and a second encoder circuit connected to the first encoder circuit to receive the compressed block of data from the first encoder circuit. The second encoder circuit is configured to further compress the compressed block of data according to a codebook. The codebook is based on a distribution of data of a prior block of data or a distribution of data of a portion of the block of data that is less than the block of data. The operation of the second encoder circuit overlaps with the operation of the first encoder circuit to achieve high throughput and avoid the need for a large block of memory (e.g., SRAM) to occupy the data in flight until the second encoder circuit can start.