Patents Assigned to Western Digital Technologies, Inc.
  • Patent number: 10732878
    Abstract: One aspect of a storage device includes a non-volatile memory (NVM) comprising a plurality of memory locations each associated with a physical address, where the NVM is configured to store a logical-to-physical (L2P) mapping table associating a logical address with each of the physical addresses of the NVM; and a controller configured to support a scratchpad session by allocating one or more of the memory locations as scratchpad memory for a host, where the controller is further configured to disable updates to the L2P mapping table for the one or more memory locations allocated to the scratchpad memory across power cycles during the scratchpad session.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: August 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventor: Ramanathan Muthiah
  • Patent number: 10732893
    Abstract: A system and method improve the performance of non-volatile memory storage by facilitating direct memory access (DMA) transfers between a remote host and a non-volatile memory based storage system, such as a flash memory based data storage device (e.g., a solid state drive (SSD)). In conjunction with reading from and writing to non-volatile memory storage, a memory buffer on the non-volatile memory system is allocated, and a read or write command is translated to point to the allocated buffer. Thereafter, read and write operations may be performed through a controller, such as a non volatile memory express (NVMe) controller, using remote direct memory access (RDMA) transfers, thus bypassing time consuming processor steps of buffering data to main memory and allowing bi-directional throughput to reach network and SSD speeds.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: August 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Vladislav Bolkhovitin, Warren Fritz Kruger
  • Patent number: 10732897
    Abstract: A method and apparatus for operating a solid state drive is disclosed comprising receiving at least two commands from a host requiring an action by the solid state drive in a preliminary order, ordering the at least two commands based upon a quality of service classification for the at least two commands to a final order and executing the at least two commands on the solid state drive in the final order, wherein an operational parameter of the solid state drive is modified by at least one of the at least two commands.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: August 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Shay Benisty
  • Patent number: 10730128
    Abstract: A solder ball bonding (SBB) tool includes a rotatable feed plate for transporting solder balls from a translatable solder ball reservoir to a nozzle unit, which is a position at which a laser light source can irradiate and thus melt the solder balls. The SBB tool includes a gap between the reservoir and the feed plate positioned over the reservoir, and a feed mechanism coupled with the reservoir, where the feed mechanism is driven by a pressurized gas to translate the reservoir upward across at least a portion of the gap in preparation for movement of a solder ball to the feed plate and downward in preparation for rotation of the feed plate after a solder ball is moved to the feed plate. The gap may have a maximum size that exceeds a nominal size of the solder balls contained in the reservoir.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: August 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yusuke Matsumoto, Kenichi Murata
  • Patent number: 10732896
    Abstract: A method and apparatus for optimizing read operations during a control sync operation on a data storage device are disclosed. The data storage device contains a management table used for mapping memory addresses to a non-volatile memory. A control sync operation makes a copy of the management table to the non-volatile memory. The control sync operation is non-blocking—the sync operation allows read and write operations in parallel with making a copy of or updating the management table. During the control sync operation, the read operations are optimized through a CUQ and an overlap range table. The CUQ may act as a temporary management table while also containing updates to be consolidated to the management table. The overlap range table is used to allow skipping searches within the CUQ by identifying then mapping entries that reside within CUQ.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: August 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Karin Inbar, Michael Micha Ionin, Einat Lev
  • Patent number: 10732838
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for hybrid dual write. An apparatus includes a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks. An apparatus includes a hybrid writing component. A hybrid writing component includes a single level writing circuit that writes data to a plurality of single level cell blocks. A hybrid writing component includes a multi level writing circuit that copies data from a plurality of single level cell blocks to a plurality of multi level cell blocks. A hybrid writing component includes a grouping circuit that directs a single level writing circuit to write data corresponding to a first logical group to a set of single level cell blocks of a plurality of single level cell blocks.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: August 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Noor Mohamed, Athira Kanchiyil, Sharad Gupta, Arunkumar Mani, Silky Mohanty, Arun Kumar Shukla
  • Patent number: 10733100
    Abstract: Embodiments of the present disclosure generally relate to a target device handling overlap write commands. In one embodiment, a target device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a random accumulated buffer, a sequential accumulated buffer, and an overlap accumulated buffer. The controller is configured to receive a new write command, classify the new write command, and write data associated with the new write command to one of the random accumulated buffer, the sequential accumulated buffer, or the overlap accumulated buffer. Once the overlap accumulated buffer becomes available, the controller first flushes to the non-volatile memory the data in the random accumulated buffer and the sequential accumulated buffer that was received prior in sequence to the data in the overlap accumulated buffer. The controller then flushes the available overlap accumulated buffer, ensuring that new write commands override prior write commands.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: August 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Shay Benisty
  • Patent number: 10732869
    Abstract: Non-limiting examples of the present disclosure relate to execution of in-situ manufacturing for a data storage device. In-situ manufacturing is on-location configuration of a data storage device within an operational environment in which a data storage device is being deployed. In-situ manufacturing occurs at any point after a data storage device is shipped from a manufacturing plant or factory. When an operational environment of the data storage device is known, parameters of the data storage device can be configured (or re-configured) on-location within an operational environment to optimize capacity management as well as performance of the data storage device.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: August 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Austin Striegel, Timothy Lieber
  • Patent number: 10732871
    Abstract: A method of transitioning between a sleep mode for a storage device to reduce power consumption and to increase responsiveness includes collecting one or more recent parameters related to host-storage device workload. The host-storage device workload is correlated to project a next host idle time. A transition between a storage sleep mode is determined.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: August 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Shay Benisty, Judah Gamliel Hahn, Ariel Navon, Alexander Bazarsky, Alon Marcu
  • Patent number: 10732864
    Abstract: A data storage device includes a power input port, a nonvolatile memory module, a controller for the nonvolatile memory module, and a power analyzer electrically coupled to the power input port. The power analyzer is configured to receive input power from the power input port, determine power data associated with the data storage device based on the input power, and store the power data in a memory of the power analyzer.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: August 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Sahil Sharma
  • Patent number: 10732877
    Abstract: In one embodiment, there is a method for managing data in a storage device comprising a non-volatile memory having a plurality of jumbo blocks, each jumbo block having a separate and distinct physical block address. The method comprises performing a folding operation data associated with a first virtual address from a plurality of Single Level Cell (SLC) jumbo blocks of the non-volatile memory to one Multilevel Cell (MLC) jumbo block of the non-volatile memory, receiving a read request to read data associated with a first logical block address, identifying that the first virtual address is associated with the first logical block address, determining whether a jumbo block associated with the first logical block address meets pre-SLC-overwrite criteria. In response to a determination that the jumbo block associated with the first logical block address meets pre-SLC-overwrite criteria, reading data from the SLC jumbo block associated with the first virtual address.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: August 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Raghavendra Gopalakrishnan, Nicholas Thomas, Karin Inbar
  • Patent number: 10732900
    Abstract: The present disclosure generally presents a method and apparatus to provide a bounded latency, where a device would report “non-service” of a command at the defined system level timeout or earlier if the device was unable to successfully return the data to the host.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: August 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Neil Hutchison, Peter Grayson, Xinde Hu, Daniel Helmick, Rodney Brittner
  • Patent number: 10732899
    Abstract: Exemplary methods and apparatus are provided to reduce read retry latency within solid state devices (SSDs) with non-volatile memories (NVMs). The reduction in read retry latency may be accomplished in some examples by prioritizing read recovery of a regular codeword over an irregular codeword for a cross-die logical page, irrespective of the location in the page with read errors. In an illustrative example, a processor (a) performs a read retry for a second codeword by setting a read voltage level to a first level for a first die, then advancing through a read retry table for the second die until the second codeword is read successfully, and (b) then performs a read retry for the first codeword by setting a read voltage level for the second die to a second level, then advancing through a read retry table for the first die until the first codeword is successfully read.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: August 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Xiaoheng Chen
  • Patent number: 10733098
    Abstract: Example storage systems, storage devices, and methods provide a write group journal for identifying incomplete writes. Related write request indicators are stored in a non-volatile journal in a solid state drive to identify a related write group and indicate whether the related write group has been stored in storage locations corresponding to physical page addresses. An event notification is sent to a host system when the related write request indicator indicates that the group was incomplete at the time of a data loss event.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: August 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Kapil Sundrani, Karimulla Sheik
  • Patent number: 10733136
    Abstract: Semiconductor substrate sections joined by an integral flexible cable are utilized to form a device comprising a connector. The connector can be surface mounted on through-holes and soldered for enhanced robustness.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: August 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventor: Khoon Guan Tee
  • Patent number: 10733061
    Abstract: Systems and methods are disclosed for accessing data on a storage system. An apparatus, such as a data storage device or a computing device, may include a memory configured to store data. The apparatus is configured to determine an importance level for a file to be stored in the storage system. The data storage system includes one or more private storage clouds and one or more public storage clouds. The apparatus is also configured to generate a set of recovery data chunks based on the file and the importance level. The apparatus is further configured to store the set of recovery data chunks in the set of public storage clouds. The apparatus is further configured to store at least a portion of the file in the private storage cloud.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: August 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jun Xu, Wei Xi, Guoxiao Guo, Eric Bjornson, Jie Yu, Ling Chih Wei
  • Patent number: 10734071
    Abstract: Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: August 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mostafa El Gamal, Niranjay Ravindran, James Fitzpatrick
  • Patent number: 10735031
    Abstract: A method and apparatus for obtaining data from a memory, estimating a probability of data values of the obtained data based on at least one of a source log-likelihood ratio and a channel log-likelihood ratio, wherein each bit in the obtained data has an associated log-likelihood ratio, determining at least one data pattern parameter for the data and performing a decoding process using the at least one data pattern parameters to determine a decoded data set.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: August 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Dudy David Avraham, Eran Sharon, Omer Fainzilber, Alexander Bazarsky, Stella Achtenberg
  • Patent number: 10734084
    Abstract: A non-volatile storage system comprises non-volatile memory cells arranged in physical blocks, and one or more control circuits in communication with the non-volatile memory cells. The one or more control circuits are configured to write data to a physical block of the non-volatile memory cells with a scheme to reduce read disturb if a logical block associated with the physical block has a read intensity greater than a threshold.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: August 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Narayan Kuddannavar, Swaroop Kaza, Sainath Viswasarai
  • Patent number: 10734079
    Abstract: The disclosure relates in some aspects to a read scrub design for a non-volatile memory that includes a block comprising N wordlines partitioned into a first sub-block comprising a first subset of the N wordlines and a second sub-block comprising a second subset of the N wordlines different than the first subset. In some aspects, the disclosure relates to detecting a trigger event associated with a read command performed on the first sub-block. A target sub-block test is then performed in response to a detection of the trigger event to determine whether to add the first sub-block to a read scrub queue. If the first sub-block is added to the read scrub queue, a sister sub-block test is then performed to determine whether to add the second sub-block to the read scrub queue.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: August 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Srinivasan Seetharaman, Sourabh Sankule, Piyush Girish Sagdeo, Gautam Ashok Dusija, Chris Nga Yee Yip