Abstract: The present disclosure generally relates to improving memory management. When valid mSets are relocated via mBlock compaction, the uLayer will have some updates for the mSet and consolidation of the mSet will write the mSet to mBlock once more. The disclosure herein reduces the impact of the problem that the same more frequently updated mSets uRegions are consolidated many times and written to flash where the less updated mSets uRegions become trapped uRegions in the uLayer reducing the uLayer capacity and efficacy. The disclosure provides guidance on how to synchronize the uLayer consolidations efficiently and preventing trapping of unused uRegions in the uLayer that reduces the uLayer capacity and efficiency. The synchronizing is between the uLayer consolidation to the mLayer and the mBlock compaction process such that the smaller uLayer efficacy will not be reduced due to trapped uRegions that are less frequently updated.

Abstract: The present disclosure generally relates to optimizing memory storage performance and power usage. Read operations from flash memory are comprised of a sense operation and a read transfer operation. Usually, these two operations are performed in parallel to achieve high read performance. However, these two operations typically do not take the same amount of time, leading to inefficiencies. By measuring sense busy time, the read transfer clock may be set accordingly so the two operations are equal in time. In so doing, the system will be optimized from both a performance and power consumption point of view.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command to read data from the memory device or a write command to write data to the memory device from a host device, determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists in a hardware module of the plurality of hardware modules, and execute a bottleneck release operation when the bottleneck exists in the data/control path between the host device and the memory device, wherein the bottleneck release operation is dependent on whether the bottleneck exists in the input queue. The bottleneck release operation includes changing a clock of the hardware module, moving the command to a different hardware module configured to process the command, and combinations thereof.

Abstract: The present disclosure generally relates to validating memory devices. Rather than using debug hardware (HW) to consume, record, and decode firmware (FW) events, standard non-volatile memory express (NVMe) asynchronous event request (AER) and NVMe asynchronous event notification (AEN) is used. The NVMe AER results in initiating a particular function to be performed by a device under test (DUT) and triggering a cross feature (CF) that should at least partially overlap in time with the particular function. Using NVMe AER and AEN will eliminate the need for debug HW, reduce FW custom logic, and reduce latency.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command to read data from the memory device or a write command to write data to the memory device from a host device, determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists in an input queue corresponding to a hardware module of a plurality of hardware modules, and execute a bottleneck release operation when the bottleneck exists in the data/control path between the host device and the memory device, wherein the bottleneck release operation is dependent on whether the bottleneck exists in the input queue. The bottleneck release operation includes changing a clock of the hardware module, moving the command to a different hardware module configured to process the command, and combinations thereof.

Abstract: The present disclosure generally relates to improved event filtering, debugging, and flow communication through a flow identifier. Rather than sending messages or events with no identity or with local identity (that is identity that has meaning only to a few modules, and not to all the modules), this disclosure suggests adding a flow identifier to each message or event. The flow identifier is at least two bits added to each message to be later identified when needed. A first message is sent to a HW or FW module. At either the HW or FW module an event will be generated. When the event is generated the flow identifier will be added to the event. The HW or FW module will then send the generated events along with the flow identifier to the TBRAM. Once received, the TBRAM will send the events along with the flow identifier to a PC.

Abstract: Embodiments of the present disclosure relate to a cobalt-boron (CoB) layer for magnetic recording devices, memory devices, and storage devices. In one or more embodiments, the CoB layer is part of a spin-orbit torque (SOT) device. In one or more embodiments, the SOT device is part of an SOT based sensor, an SOT based writer, a memory device (such as a magnetoresistive random-access memory (MRAM) device), and/or a storage device (such as a hard disk drive (HDD) or a tape drive). In one embodiment, an SOT device includes a seed layer, and a cap layer spaced from the seed layer. The SOT device includes a spin-orbit torque (SOT) layer, and a nano layer (NL) between the seed layer and the cap layer. The SOT device includes a cobalt-boron (CoB) layer between the seed layer and the cap layer, and the CoB layer is ferromagnetic.

Abstract: A stack of alternating layers of dielectric and conductive materials are formed on a substrate. A first portion of the stack of alternating layers forms a plurality of blocks of NAND memory. A second portion of the stack of alternating layers forms a configurable capacitor structure. The configurable capacitor structure is configurable to form one or more capacitors of configurable capacitance.

Abstract: A combined semiconductor device package includes a first semiconductor device package having a first semiconductor chip housed within a first enclosure, and a first substrate coupled to the first enclosure. The first substrate includes first solder balls and second solder balls, each in electrical communication with the first semiconductor chip. The first semiconductor device further includes conductive pads directly coupled to the first substrate. The conductive pads are in electrical communication with the first and second solder balls. The combined semiconductor device package further includes a second semiconductor device package having a second semiconductor chip housed within a second enclosure, and third solder balls in electrical communication with the second semiconductor chip, and coupled to the conductive pads of the first semiconductor device package.

Abstract: Example control circuitry, data storage devices, and methods to provide a spiral data track format that is different from the underlying servo track format are described. The data storage device may include a storage medium configured with a plurality of tracks in at least one continuous spiral pattern and a head actuated over the storage medium. The data tracks may be written to the storage medium with track lengths that are different than a single revolution of the storage medium.

Abstract: Various illustrative aspects are directed to a data storage device comprising one or more disks, an actuator arm assembly comprising a voice coil motor (VCM), the VCM configured to operate in a first mode and a second, different mode, wherein the first mode corresponds to at least a first and a second setting, and a control circuitry configured to cause the VCM to seek towards a target track in the first mode using the first setting for a first duration, control transition of the VCM from the first to the second setting in the first mode, cause the VCM to seek towards the target track using the second setting for a second duration, and control transition of the VCM from the first to a second mode, wherein controlling the transitioning comprises seeking the VCM toward the target track in the second mode for a third duration.

Abstract: Disclosed herein are devices, systems, and methods that can improve the SNR of nanopore measurements by mitigating the effect of parasitic capacitance between the sense electrode and the counter electrode. In some embodiments, a feedback circuit is used to inject a charge into the sense electrode to at least partially cancel the parasitic capacitance between the sense electrode and the counter electrode. In some embodiments, bootstrapping of a signal from the amplifier output or from the sense electrode is used to inject a charge on the counter electrode to substantially cancel the parasitic capacitance.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data, group a plurality of KV pair data based on a data clustering value, aggregate the grouped plurality of KV pair data, and program the aggregated plurality of KV pair data to the memory device. A length of the KV pair data is less than a size of a flash management unit (FMU). The KV pair data includes a key and a value. Each KV pair data of the plurality of KV pair data has a length less than the size of the FMU. The received KV pair data is stored in a temporary location and grouped together in the temporary location. The grouping is based on a similarity of characteristics of plurality of KV pair data.

Abstract: The present disclosure generally relates to a tape head and a tape head drive including a tape head. The tape head comprises at least one same gap verify (SGV) module comprising a closure, a substrate, and a plurality of write transducer and read transducer pairs disposed between the substrate and the closure. The write transducer and the read transducer of each pair are aligned in a first direction and spaced a distance in the downtrack direction of about 5 ?m to about 20 ?m. A first overcoat is disposed over each write transducer at a media facing surface (MFS), and a second overcoat is disposed over each read transducer at the MFS. The first and second overcoats may comprise different materials, and are deposited during different processes.

Abstract: The present disclosure generally relates to improved unaligned deallocated logical block transfer. Rather than stalling the data-path in unaligned deallocated LBA scenarios, the data-path will work regularly while ignoring the unaligned deallocated indication. The old and non-valid data received for the unaligned deallocated LBA will be written to the host. The device controller will detect the unaligned deallocated LBA and overwrite the data with other values such as 0's or 1's as specified in the standard. The implementation increases the performance of unaligned deallocated commands and the endurance of the NVM. The implementation also simplifies the logic implemented in the device controller.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. When a copy command is received by the controller from a host device, the controller reads the relevant data from one or more first locations of the memory device. The data is the processed by an Rx path, where the data is decoded, decrypted, and verified. Rather than providing the data back to the host device or being made available to the host device, a copy accelerator loops the data from the Rx path to a Tx path, where protection information is generated and added to the data and the data is encrypted and encoded. The data is then programmed back to the memory device in a second location. By using the copy accelerator, a latency associated with performing copy command operations and other data management operations may be decreased.

Abstract: The present disclosure generally relates to magnetoresistive (MR) devices. The MR device comprises a synthetic antiferromagnetic (SAF) layer that increases exchange coupling field, and in turn, less magnetic noise of such devices. The MR device comprises a first ferromagnetic (FM1) layer and a second ferromagnetic (FM2) layer, in between which is an SAF spacer of RuAl alloy having a B2 crystalline structure which may grow epitaxial on BCC (110) or FCC (111) textures, meaning that the (110) or (111) plane is parallel to the surface of MR device substrate. Further, amorphous layers may be inserted into the device structure to reset the growth texture of the device to a (001), (110), or (111) texture in order to promote the growth of tunneling barrier layers or antiferromagnetic (AF) pinning layers.

Abstract: Apparatuses, systems, and methods for low latency parity for a memory device include a controller configured to accumulate, in a memory buffer, combined parity data for a plurality of regions of memory of a memory device in response to write operations for the plurality of regions of memory. The controller is configured to perform a recovery operation for a region of memory in response to determining that a latency setting for the region satisfies a latency threshold. The controller is configured to service a read request for data from the region based on a recovery operation to satisfy the latency setting.