Abstract: A data storage device including, in one implementation, a non-volatile memory device having a memory block including a number of memory dies, and a controller coupled to the non-volatile memory device. The controller is configured to monitor a temperature of the data storage device and determine whether the monitored temperature exceeds a first temperature threshold. The controller is also configured to perform a default thermal throttling operation based on the monitored temperature exceeding the first temperature threshold, determine whether the monitored temperature exceeds a second temperature threshold, and perform a customized thermal throttling operation based on the monitored temperature exceeding the second temperature threshold.

Abstract: Aspects of a storage device are provided that provide power control and power loss handling in a RAID system. The storage device may include a memory, a controller coupled to the memory, a power management circuit coupled to the memory and the controller, and a rechargeable battery coupled to the power management circuit. The controller may receive power supplied by a RAID controller, receive a notification of a loss in power supplied to another storage device, and cause the power management circuit to detect a charge of the rechargeable battery in response to the notification. The power management circuit may also detect another loss in power supplied by the RAID controller, cause the controller to send a message to the RAID controller indicating the loss in power, and receive power from the RAID controller in response to the message. As a result, UGSDs in RAID may be detected and addressed.

Abstract: The present disclosure generally relates to a multi-disk drive comprising a plurality of media surfaces and a plurality of heads, wherein a head of the plurality of heads is configured to be actuated over each surface of the plurality of media surfaces. The multi-disk drive further comprises control circuitry configured to write data to a first media surface of the plurality of media surfaces using a first head of the plurality of heads, and after all of an available memory of the first media surface has been filled, write data to a second media surface of the plurality of media surfaces using a second head of the plurality of heads. The control circuitry is further configured to permanently disable write access to one or more media surfaces of the plurality of media surfaces, while continuing to permit read access to the plurality of media surfaces.

Abstract: Aspects of a storage device including a memory and a controller are provided. The controller may convert unaligned write commands into aligned write commands and generate unaligned information associated with the unaligned write commands. In some aspects, the unaligned information indicates offset information for each unaligned write command. The controller may accumulate a threshold size of aligned write command transfer sizes in an aggregation command queue and fetch pre-pad or post-pad data for each unaligned write command in parallel based on the aggregation command queue having accumulated the threshold size of aligned write command transfer sizes. The controller may transfer host data for each unaligned write command to a data buffer at a corresponding offset within the data buffer based on the unaligned information. The controller may generate aligned data using the pre-pad or post-pad data combined with the host data and program the aligned data into a memory die.

Abstract: Aspects of a storage device are provided that handle pairing and atomic processing of fused commands received from submission queues based on data structures such as a linked lists which the controller respectively associates with each submission queue. A memory of the storage device includes a plurality of data structures each associated with a different submission queue. A controller of the storage device receives a first command for a fused operation from a submission queue, stores the first command in a data structure, receives a second command for the fused operation from the submission queue, determines whether the second command corresponds to the fused operation, stores the second command in the data structure in response to the determination, and performs the fused operation in response to storing the second command. As a result, fused command handling may be achieved with minimal impact to queue arbitration logic and command latency.

Abstract: Error correction code (ECC) coding for key-value data storage devices. In one embodiment, a controller includes a memory interface configured to interface with a memory; an ECC engine configured to perform ECC coding on data stored in memory; a controller memory including a flash translation layer and a namespace database; and an electronic processor. The electronic processor is configured to receive data to be stored, separate the data into a plurality of sub-code blocks, and allocate parity bits to each sub-code block of the plurality of sub-code blocks.

Abstract: Data blocks may be optimized and managed in a mixed mode that utilizes a single-level cell (SLC) mode in combination with higher-density memory modes to promote full block utilization and to increase overall cycles of the data blocks. A data block cycling process in the mixed mode can place a data block in a higher-density memory mode that includes a multi-level cell (MLC) mode, a triple-level cell (TLC) mode, or a quad-level cell (QLC) mode, if the SLC cycle count of the data block is relatively higher as compared to other data blocks. Similarly, in the mixed mode, a data block may be placed in the SLC mode to store parity data or intermediate data if the corresponding TLC cycle count is relatively higher than other data blocks. Data clocks cycles may also be evenly distributed in the mixed mode, thereby balancing the mixed mode usage across all data blocks.

Abstract: A client device includes at least one memory configured to be used at least in part as a shared cache in a distributed cache. A network interface of the client device is configured to communicate with one or more other devices on a network each configured to provide a respective shared cache for the distributed cache. A Non-Volatile Memory express (NVMe) controller of the client device receives a command from a processor to access data in the shared cache and executes a program to use data read from the shared cache or data to be written to the shared cache to perform at least one computational operation. In another aspect, data is accessed in the shared cache using a kernel and data read from the shared cache or data to be written to the shared cache is used to perform at least one computational operation by the kernel.

Abstract: A disk clamp for a hard disk drive, configured to clamp disk media to a spindle, includes multiple protrusions extending from a surface of a bottom side and configured to contact a disk medium at multiple contact positions in response to application of a clamping load. The protrusions may be annular protrusions circumscribing a disk clamp hub, where the height of an inner protrusion may be less than the height of an outer protrusion to inhibit coning of the top disk medium, and the protrusions may be positioned so that an equivalent contact radius corresponding to contact radii of the inner and outer annular protrusions is at a position halfway between the inner and outer diameters of the disk spacers to inhibit coning of the middle disk media.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine a maximum bandwidth of an interface, allocate a portion of the maximum bandwidth to one or more tenants, either: determine a maximum data transfer size (MDTS) setting based on quality of service (QoS) requirements, determine an aggregated queue depth (QD) setting based on QoS requirements, or determine a combined MDTS and aggregated QD setting based on QoS requirements, and provide the determined settings to the one or more tenants.

Abstract: The present disclosure generally relates to data storage devices, such as solid state drives (SSDs), specifically utilizing the data storage device memory in the execution of host commands. A controller is configured to receive a command pointer or a data chunk from a host device, mark a destination used for the command pointer or the data chunk, determine whether a last chunk of the command pointer or the data chunk has been received, and determine whether the command pointer or the data chunk uses an illegal combination of locations after determining that the last chunk of the command pointer has been received. The controller is further configured to return an error message to the host device upon determining that the command pointer or the data chunk uses an illegal combination of locations.

Abstract: Various devices, such as storage devices or systems are configured to efficiently manage and determine control table sets. Such a device may include a processor, a memory array including a plurality of memory devices which include a plurality of control table sets stored in a plurality of regions, and a control table set determination logic configured to: receive a command from a host device associated with logical to physical address mapping updates, determine a control table set of the plurality of control table sets associated with the command, determine a region of the plurality of regions associated with the determined control table set, determine a position in the control table set in the determined region associated with the command, generate additional control table sets upon a first determination that the position is not vacant, and store the command in the generated additional control table sets.

Abstract: Aspects of a storage device provide an optimized data relocation scanning process which significantly reduces a number of page reads performed during a block relocation scan by consolidating logical addresses for multiple FMUs in a single FMU. The storage device includes a memory comprising a block including pages and FMUs, and a controller that is configured to store, in one of the FMUs, logical addresses for multiple FMUs. The controller is further configured, in response to a data relocation command, to read the logical addresses from the FMU, to determine at least one of the read logical addresses is mapped to a current FMU in a L2P mapping table, and to relocate data stored at the valid logical addresses in response to the determination. As a result, latency and power consumption associated with data relocation may be significantly reduced and storage device performance may thus be improved.

Abstract: Disclosed herein are improved methods and systems for sequencing nucleic acid that exploit the temperature-dependence of the emitted intensity of fluorescent dyes. The temperature of the sequencing reaction is adjusted during each sequencing cycle, and the emission, or lack of emission, of light meeting or exceeding a threshold by the fluorescent dyes at different temperatures, or within different temperature ranges, is used to detect the fluorescent labels of the incorporated dNTPs and thereby sequence the nucleic acid. The disclosed methods enable a determination of the dNTP incorporated at any given site with a reasonable number of chemistry steps without the complex optics necessary for prior-art systems.

Abstract: The present disclosure generally relates to a tape drive. The tape drive comprises a first tape head and a second tape head linearly aligned with one another, where the first tape head and the second tape head are configured to concurrently operate. The first tape head and the second tape head each comprise a plurality of write transducers, a plurality of read transducers, and a plurality of servo transducers. The tape drive further comprises a first actuator coupled to the first tape head and a second actuator coupled to the second tape head. The first and second actuators are configured to independently tilt and move the first and second tape heads, respectively. Tilting and moving the first and second tape heads individually enables the tape drive to compensate for non-linear tape dimensional stability effects.

Abstract: The present disclosure is generally related to a tape drive comprising a tape head and a controller coupled to the tape head. The tape head comprises one or more modules, each module comprising a plurality of write heads aligned in a first row, a plurality of read heads aligned in a second row parallel to the first row, and at least four first servo heads aligned in the second row. Two or more first servo heads of the at least four first servo heads are configured to concurrently read first servo data from a first servo track. The controller is configured to concurrently process the first servo data, to compute the position of the tape head based on a known spacing between the at least two servo heads, and to dynamically adjust a position of the tape head based on the processed first servo data.

Abstract: Embodiments described herein provide a linked XOR flash data protection scheme for data storage devices. In particular, the embodiments described herein provide a data storage controller with a memory space efficient XOR-based flash data protection/recovery algorithm with minimal flash block space overhead and support of recovery from full plane failure with neighbor planes disturb (NPD) in a single word line. Additionally, the embodiments described herein provide a reduced flash block space dedicated for XOR parity buffers storage by a factor of a number of planes per die without losing the capability to recover from NPD.

Abstract: Disclosed are systems and methods for accelerating commands from accelerators in data storage devices using accelerator queues. A data storage device includes accelerator interfaces, each accelerator interface couples a controller to a respective accelerator. The device also includes a device memory comprising one or more memories and one or more sets of queues. Each set of queues corresponds to a respective memory, at least one queue is configured to queue one or more tasks associated with an accelerator, and each queue is associated with a respective priority level of a plurality of priority levels. A controller is configured to: receive an accelerator command, identify a first memory corresponding to a task for the accelerator command; and enqueue the task to a first queue corresponding to the first memory, the first queue configured to queue one or more tasks associated with the first accelerator corresponding to the first accelerator interface.

Abstract: Technology is disclosed herein for handling of mixed random read and sequential read command sequences. Plane read commands are formed from one or more sequential read commands. A sequential read command may be split into multiple plane read commands at plane boundaries. The plane read commands are submitted to the respective planes as asynchronous independent plane read commands. Random read commands may be submitted to the planes as asynchronous independent plane read (AIPR) commands on par with the split sequential read commands. Therefore, AIPR may be used for both sequential read commands and random read commands. Submitting a split sequential read command to one or more planes while one or more other planes are performing a random read command can significantly improve performance.

Abstract: The present disclosure generally relates to improving programming to data storage devices, such as solid state drives (SSDs). A first memory device has a first XOR element and a second memory device has a second XOR element. The ratio of the first XOR element to the capacity of the first memory device is substantially smaller than the ratio of the second XOR element to the capacity of the second memory device. A read verify operation to find program failures is executed on either a wordline to wordline basis, an erase block to erase block basis, or both a wordline to wordline basis and an erase block to erase block basis. Because the program failures are found and fixed prior to programming to the second memory device, the second XOR element may be decreased substantially.