Abstract: Instead of using a bandwidth limiter for bandwidth allocation in an SSD, a dummy virtual function (VF) is used to transfer internal operations. A centralized logic such as the bandwidth limiter is incorporated in the device controller. This logic is responsible for controlling the bandwidth between the hosts. The logic is not just responsible for data transfers triggered by the hosts, but also for data transfers triggered by the device in internal operations such as garbage collection. In order to control the traffic trigged by internal operations, a dummy VF is created along with dummy submission queues. The internal operations are queued in the dummy submission queues, while the bandwidth limiter is responsible for the performance rate. Using this approach, bandwidth allocation is balanced between the hosts and SSD.

Abstract: Technology is disclosed herein for a shallow erase for erase pool management. The memory system performs a shallow erase of a block of memory cells prior to placing the block in a shallow erase pool. The block may remain in the shallow erase pool for a substantial time with little to no risk of damage to the memory cells. The memory system completes the erase of the block at a later time. The memory system may select the block from the shallow erase pool when the system determines there is a need for another fully erased block. The erase voltage used for the shallow erase may be substantially lower in magnitude than the erase voltage used to complete the erase.

Abstract: A non-volatile storage apparatus comprises a non-volatile memory divided into blocks, with each block divided into regions. Each region of a same block includes a plurality of non-volatile memory cells controlled by a separate drain side (or different type of) select line for the region such that different regions of a same block are controlled by different drain side (or different type of) select lines. The non-volatile storage apparatus is configured to concurrently program memory cells in multiple regions.

Abstract: When performing a read process, a non-volatile memory first performs a pre-read sensing of the condition of memory cells connected to neighbor word lines. While applying a first word line voltage associated with a first programmed data state to the selected word line, the memory system performs two sensing operations for the first programmed data state on selected memory cells that have neighbor memory cells on the neighbor word lines in a first condition and perform two sensing operations for the first programmed data state on selected memory cells that have neighbor memory cells on the neighbor word lines in a second condition. Based on that sensing, the data being stored in the set of selected memory cells is determined. In some embodiments, at least one of the two sensing operations for each condition includes sensing soft bit information that improves the data decoding process.

Abstract: Instead of handing each hot LBA separately, a hot LBA tracker is used to handle hot LBAs. As a command arrives, the controller classifies the command. If the command is classified as a hot LBA, then the hot LBA tracker will store the hot LBA in a separate location from where the executed commands are stored. In doing so, the hot LBA tracker will store completion information without executing the hot LBA. The hot LBAs that have a stored completion, but are not executed, are considered “skipped” hot LBAs. Once the controller determines that the hot LBA needs to be executed, the controller will execute the most recent hot LBA. After execution of the most recent hot LBA, the controller sends a completion for the most recent hot LBA and “skipped” hot LBAs.

Abstract: To reduce power consumption and circuitry requirements, the following presents an “unmatched” data output architecture, in which the clock path does not mimic the data path. To provide proper data transfers in the data output path, the clock signal is tuned at points of the clock path, such as for data transfers from internal data buses to FIFOs and from the FIFO though the multiplexers to the input/output pads. An amount of timing offset is introduced in the generation of internal transfer clocks, which can be determined as part of a valid data window training process that can be performed by the controller, such as part of the power up process.

Abstract: A storage device may be coupled to a host device and the storage device may support a host performance booster (HPB) feature. A controller on the storage device may execute a background relocation operation. During the background relocation operation, the controller may identify a block to relocate data from. The controller may also determine that a relocation system threshold has not been reached. The controller may execute a source selection algorithm configured to minimize HPB entry inactivation resulting from data relocation. The source selection algorithm may include a criterion to enable the controller to select a source block for relocation.

Abstract: Technology is disclosed herein for simultaneous lower tail program verify with upper tail verify. The memory system may apply a reference voltage to a word line following applying a program voltage to the word line. The memory system senses the first set of memory cells targeted for a first data state and the second set of memory cells targeted for a second data state. The memory system determines whether memory cells in the first set have a Vt greater than a maximum target Vt for the first data state based on the sensing of the first set of memory cells. The memory system also determines whether memory cells in the second set have a Vt less than a minimum target Vt for the second data state based on the sensing of the second set of memory cells.

Abstract: To improve memory cell endurance and erase times for non-volatile memories, such as NAND memory, a sub-block based adaptive erase pulse is used. In a memory structure where the array is composed of blocks that have multiple sub-blocks, after applying an erase pulse to an erase selected block, one of the sub-blocks is erased verified and, if it fails to verify, the next erase pulse's duration is tuned based on the number of memory cells of that sub-block that fail to verify. If the first verified one of the sub-blocks verifies, the other sub-blocks of the erase selected block are erased verified, with the next erase pulse's duration tuned based on the number of the other sub-blocks that fail to verify.

Abstract: Key value (KV) pair data includes a key and a value, where the key addresses the value. The value may include one or more flash management units (FMUs). Because the value is read in order, sequentially from one FMU to a next FMU, end-to-end (E2E) protection of the value may be optimized and improved. E2E protection may including using checksum signatures, of which cyclic redundancy code (CRC) signatures are but one example, to ensure that corrupted data is not returned to a host device. Optimizing checksum signatures used to protect the value may include generating an aggregated checksum signature for each FMU based on a current FMU and each previous FMU of the value or only generating a single checksum signature for an entirety of the value. Thus, characteristics of the value may be taken advantage of in order to improve and optimize E2E protection.

Abstract: Rather than using low power mode since there is no indication of a sleep mode type to the data storage device, the sleep mode type is inferred by the data storage device, or supplied by the host. In so doing, the sleep type communication is improved. After the system returns power to the data storage device, there may be a read workload, depending on the sleep type. The workload is characterized by a low-queue depth (QD) sequential read from a specific area of the storage medium that was written to just prior to shut down. In response to inference or host cue, the data storage device will modify an operation so that data storage device is optimized to the sleep mode type, resulting in improved performance and power consumption.

Abstract: Multiple non-volatile memory dies are tested to identify word lines that have a first reliability and word lines that have a second reliability. Word lines that have the first reliability are designated to store data at a first number of bits per memory cell. Word lines that have the second reliability are designated to store data at a second number of bits per memory cell. The second number of bits per memory cell include more bits per memory cell than the first number of bits per memory cell.

Abstract: A multi-disk pack hard disk drive includes first and second spindle motor assemblies mounted one over the other on a base post. Each motor assembly may include a compact axial flux motor. The motor wiring for each may be routed within a structural cutout feature of the base post to an electrical connector at the base. A compact threaded disk clamp and motor hub interface may be implemented to further reduce the vertical height of the multi-disk pack assembly.

Abstract: Instead of using external tools for admin control operations for a device, files are used to control the device. As admin controls need to be changed, a special file is generated in the device using a file pattern generator. When the special file is written to the storage device, a file pattern engine recognizes the special file created to extract the vendor specific command. When the special file is written to the storage device, the device will recognize the special file and will perform the operation indicated in the special file. The user is able to use the special file for a single use or future use when needed. In future use cases, the special file is able to be recognized by other devices in need of the special file to execute the vendor specific command.

Abstract: More efficient memory device usage is possible by altering the memory device management. For example, when the full storage capacity of the memory device will not be used, certain portions of the memory device can be shut off and then turned on when the storage capacity is needed. When less capacity is needed, data can be consolidated and certain portions of the memory device can be shut off. Additionally, rather than operating in multilevel cell (MLC) memory, the memory device can start in single level cell (SLC) memory and transition to MLC memory over time. If there is a determination that less memory is needed, the memory device can transition from MLC memory to SLC memory. In so doing, the storage capacity of the memory device is more appropriately utilized.

Abstract: Instead of allowing an electrostatic discharge (ESD) event to cause a lost clock signal sync due effects of the ESD event causing an SSD to enter low power mode, utilizing ESD detection can be used to stop the reference clock signal to avoid involuntary low power mode. When an ESD event occurs, an ESD antenna sensor will selectivity disable sensitive signals and the reference clock signal. Once the ESD detector recognizes an ESD event has occurred, the device is able to enter freeze mode. While the reference clock signal is in freeze mode, the input signals are bypassed to avoid lost clock signal sync. Once the ESD event is done, the controller notifies the host to restart the reference clock signal and resume clock signal sync.

Abstract: During operation of a data storage device, a controller of the data storage device may initiate read/write operations based on workloads provided by a host device. When initiating the read/write operations, power consumption and the data rate of the data storage device are generally high. Over time, the data rate corresponding to the workload decreases. Thus, the power consumption may be decreased to correspond with the decreased data rate. In order to maintain a high efficiency while decreasing an amount of power utilized, the controller may duty cycle the data storage device to operate between performance states to maintain a high data rate while decreasing power consumption.

Abstract: A storage device may ensure consistent performance when executing a read command provided by a host device. The storage device executes a read instruction received from the host device and executes a background operation to manage resources on a memory device and/or perform thermal throttling on the storage device. The storage device executes a formula including an interleave ratio to interleave host read operations with the background operation based on an operation time. The storage device also uses a read temperature threshold, a preset slowdown percentage, and/or a read speed to optimize host read operations during thermal throttling and thereby limit performance degradation during read operations.

Abstract: Methods and apparatus for precise power cycle management in data storage devices are provided. One such apparatus is a data storage device that includes a non-volatile memory (NVM) and a processor coupled to the NVM. In such case, the processor is configured to determine a first peak power for a first power phase, operate the DSD at a first DSD power consumption that is less than the first peak power for the first power phase, determine a second peak power for a second power phase based on a residual power equal to a difference between a preselected average power threshold and the first DSD power consumption, and operate the DSD at a second DSD power consumption that is less than the second peak power for the second power phase.

Abstract: The present disclosure generally relates to a magnetic recording system comprising a magnetic recording head. The magnetic recording head comprises a main pole, a shield, and a spintronic device disposed between the main pole and the shield. The spintronic device comprises a field generation layer (FGL) spaced a distance of about 2 nm to about 3 nm from the main pole, a first spacer layer disposed on the FGL, a spin torque layer (STL) disposed on the first spacer layer, a second spacer layer disposed on the STL, and a negative polarization layer (NPL) disposed between the second spacer layer and the shield. The spintronic device has a length of about 17 nm to about 21. During operation, the STL has a magnetization precession of about 16 degrees to about 170 degrees, and the FGL has a magnetization precession of about 60 degrees to about 70 degrees.