Abstract: Disclosed herein are detection methods that use magnetic nanoparticles (MNPs) to allow molecules to be identified. Embodiments of this disclosure include methods of using magnetic sensors (e.g., magnetoresistive sensors) to detect temperature-dependent magnetic fields (or changes in magnetic fields) emitted by MNPs, and, specifically to distinguish between the presence and absence of magnetic fields emitted, or not emitted, by MNPs at different temperatures selected to take advantage of knowledge of how the MNPs' magnetic properties change with temperature. Embodiments disclosed herein may be used for nucleic acid sequencing, such as deoxyribonucleic acid (DNA) sequencing.

Abstract: Methods, data storage devices, and computer-readable media for setting the flying height of a recording head are disclosed. A method may set a value of a control parameter of the recording head to force a predetermined location of the recording head to be a touchdown location. The method may involve incrementally moving the recording head toward a surface of a recording media, and, using a temperature sensor of the recording head, detecting an onset of touchdown at the touchdown location as the recording head is incrementally moving toward the surface of the recording media. The method may set the fly-height control power by backing off from an initial fly-height control power value, which may be a sum of a power level at which the onset of touchdown at the touchdown location was detected and a power corresponding to the value of the control parameter.

Abstract: Aspects of a storage device including a memory and a controller are provided. The controller may determine to perform garbage collection on a superblock. During the garbage collection process, the controller will typically move the superblock into an erase pool for erasing the superblock. However, aspects of the disclosure are directed to a method of measuring a raw bit error rate (RBER) of the superblock prior to erasure. The measured RBER may be used to estimate a data retention time of the storage device and provide the customer with an early warning notification if a health metric of the storage devices reaches a threshold retention time.

Abstract: A data storage device may include a media comprising a magnetic recording layer and a heat-assisted magnetic recording (HAMR) head for writing to the magnetic recording layer, the HAMR head comprising: a waveguide, a main pole comprising a main-pole surface facing the magnetic recording layer, a near-field transducer (NFT) situated between the main pole and the waveguide, and a transparent overcoat. The NFT comprises a main body and a micropillar. The micropillar comprises a micropillar surface facing the magnetic recording layer. A first distance between the micropillar surface and the media is less than a second distance between the main-pole surface and the media. The transparent overcoat is situated on the main-pole surface and the micropillar surface.

Abstract: Technology is disclosed herein for a dynamic bitscan. The dynamic bitscan may include performing a first bitscan of a first strict subset of memory cells. Then, based on results of the first bitscan, a determination is made whether to perform a second bitscan of a second strict subset of memory cells. Prior to the bitscan(s) a verify reference voltage may be applied to both strict subsets of memory cells. Skipping the second bitscan saves considerable time. However, the second bitscan is performed at least sometimes, which increases accuracy. The first strict subset of memory cells and the second strict subset of memory cells may have different locations relative to some point in the block that contains the memory cells. The first strict subset of memory cells and the second strict subset may have different programming speeds.

Abstract: Technology is disclosed for controlling reads in a memory device supporting different types of reads having different performance times (e.g., a relatively fast read such as a globally-referenced read and a slower read such as a self-referenced read). The data out latencies of the different read types may be different to accommodate the different performance times. The memory controller may mix the different types of reads. The memory controller tracks expected usage of the data bus and schedules read commands accordingly to avoid data collisions. A countdown timer may be used to track the earliest clock cycle at which the memory device may return data for a new read command to be issued. The memory controller may record what clock cycles the data bus is projected to be occupied with data and schedule read commands based on the projected data bus occupancy to avoid data collisions.

Abstract: A plurality of control circuits are configured to individually connect to arrays that each include a plurality of non-volatile memory cells. Each non-volatile memory cell includes a programmable resistive element. Each control circuit is configured with an individual address offset. The plurality of control circuits are configured to: receive a read address from a memory controller in parallel, apply the respective individual address offsets to the read address to generate respective offset addresses, read portions of data from the respective offset addresses and send the data read from the offset addresses to the memory controller to perform Error Correction Code (ECC) decoding of the portions of data.

Abstract: In a word line leakage detection process in a NAND or other non-volatile memory device, a stress selected set of word lines have a high stress voltage applied while other parts of an array are biased to a low level. While stressing the memory array, the current drawn by the array is compared to a leakage detection current that increases in amplitude. For example, this can be done by mirroring the array current and comparing this with the current from a current source that increases in response to a digital input value and determining when it exceeds the mirror current, at which point the stress is discontinued. In addition to determining the amount of leakage, this approach results in low leakage word lines receiving less stress, while greater leakage result in greater amounts of stress being applied.

Abstract: A non-volatile memory is configured to transition memory cells from programmed data states with the higher ranges of threshold voltages to programmed data states with the lower ranges of threshold voltages without the transitioning the memory cells to the erased data state.

Abstract: A HAMR data storage device may include a magnetic media and a slider comprising: a main pole, a waveguide, and a near-field transducer (NFT) situated between the main pole and the waveguide, wherein an air-bearing surface (ABS) of the slider comprises a transparent overcoat layer situated over the main pole, the waveguide, and the NFT, and wherein the transparent overcoat layer has a particular thickness such that, during an operational phase of the HAMR data storage device, a gap between a media-facing surface of the transparent overcoat layer and the magnetic media is less than about 0.5 nm.

Abstract: In order to ensure that a bandwidth allocated to each tenant of a plurality of tenants of a data storage device is maintained, a controller of the data storage device may split a large read command, received from a host device, into a plurality of chunks, where each chunk corresponds to a distinct portion of the split large read command. Because the allocated bandwidth for a tenant is static, one or more chunks of the plurality of chunks, up to the allocated bandwidth, are executed, such that the bandwidth required to perform the one or more chunks does not exceed the allocated bandwidth for the particular tenant. Split information is added to the plurality of chunks in order to maintain coherency when executing the one or more chunks. Therefore, the agreed-upon allocated bandwidth for each tenant is maintained while performing large read commands requiring more bandwidth than allocated.

Abstract: A HAMR data storage device may include a magnetic media and a slider comprising: a main pole, a waveguide, and a near-field transducer (NFT) situated between the main pole and the waveguide, wherein an air-bearing surface (ABS) of the slider comprises a transparent overcoat layer situated over the main pole, the waveguide, and the NFT, and wherein the transparent overcoat layer has a particular thickness such that, during an operational phase of the HAMR data storage device, a gap between a media-facing surface of the transparent overcoat layer and the magnetic media is less than about 0.5 nm.

Abstract: Various illustrative aspects are directed to a data storage device, comprising one or more disks; an actuator mechanism configured to position a selected head among one or more heads proximate to a corresponding disk surface among the one or more disks, wherein the selected head comprises a magnetic write element and a laser generating component; and one or more processing devices. The one or more processing devices are configured to measure a magnetic saturation responsiveness of the corresponding disk surface to heat-assisted write operations using a range of values of write laser current applied to the laser generating component. The one or more processing devices are further configured to calibrate a nominal write laser current of the selected head for the corresponding disk surface based on the measured magnetic saturation responsiveness of the corresponding disk surface.

Abstract: Identifying recording disk defects in a data storage device such as a hard disk drive (HDD), for which disk defects are not previously identified, includes responsive to a first user data write request to a particular storage area of a disk medium, writing the user data to the particular storage area, reading the written user data from the particular storage area, and verifying the integrity of the user data read from the particular storage area. Upon passing, a second user data write request to the same particular storage area can be fulfilled without again reading and verifying. Upon failing, the particular storage area is marked as defective and the user data is written to a different storage area. This procedure can be repeated in response to each initial user write request to each storage area of each disk medium, foregoing the need for disk surface scanning during manufacturing.

Abstract: An apparatus is provided that includes a memory array and a control circuit. The memory array includes non-volatile memory cells each including a resistive random access memory element. The control circuit is configured to receive a read command that specifies an address of a first group of the non-volatile memory cells, use a first predetermined read reference value to perform a first read of the first group of the non-volatile memory cells to provide first read data, while performing the first read, retrieve from a memory a second predetermined read reference value corresponding to the specified address, and in response to a condition being satisfied regarding the first read data, use the second predetermined read reference value to perform a second read of the first group of the non-volatile memory cells to provide second read data.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means ramps up and applies a read voltage to unselected ones of the word lines while applying verification pulses of program verify voltages each associated with one of the plurality of data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the verify voltages associated with the plurality of data states targeted during a program-verify operation. The control means delays ramping of at least one of the selected ones of the word lines and the unselected ones of the word lines by a predetermined period of time in response to the memory apparatus operating in a predetermined mode.

Abstract: In some situations, the programming of one memory die can be suspended in favor of the programming of another memory die. This can lead to a delay in certain programming operations. To avoid this problem, a data storage device can perform dynamic logical page write ordering by determining an availability of each memory die of a plurality of memory dies and changing a programing order of the plurality of memory dies in response to the determined availability.

Abstract: A server includes at least one local memory and communicates with one or more network devices that provide an external shared memory. A kernel space of the server is used to monitor memory usage by different applications executed by the server. A memory kernel module adjusts usage of the at least one local memory and the external shared memory by the different applications based at least in part on the monitored memory usage. In another aspect, a memory access profiling server receives memory information and application usage information added to packets sent between servers and one or more memory devices. The memory access profiling server analyzes the memory information and application usage information to determine memory placement information that is sent to at least one server to adjust usage of the external shared memory.

Abstract: A non-volatile memory includes non-volatile memory cells divided into blocks, bit lines connected to the blocks, and a source line connected to the blocks. Each block includes multiple sub-blocks. Each sub-block includes multiple source side Gate Induced Drain Leakage (“GIDL”) generation transistors that are closer to the source line than the bit lines. GIDL generation transistors for each sub-block can be controlled separately from GIDL generation transistors for other sub-blocks of the same sub-block so that sub-blocks can be separately and independently erased and/or GIDL can be used to inhibit unselected sub-blocks from bring disturbed during programming.

Abstract: A non-volatile memory includes non-volatile memory cells divided into blocks, bit lines connected to the blocks, and a source line connected to the blocks. Each block includes multiple sub-blocks. Each sub-block includes multiple source side Gate Induced Drain Leakage (“GIDL”) generation transistors that are closer to the source line than the bit lines. GIDL generation transistors for each sub-block can be controlled separately from GIDL generation transistors for other sub-blocks of the same sub-block so that sub-blocks can be separately and independently erased and/or GIDL can be used to inhibit unselected sub-blocks from bring disturbed during programming.