Patents Assigned to Western Digital Technology, Inc.
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Patent number: 12170435Abstract: A data storage device may include one or more disks, an actuator arm assembly comprising one or more magnetic recording heads, a laser diode positioned inside a laser diode cavity, and one or more processing devices configured to initiate a write operation, wherein initiating the write operation comprises activating a magnetic recording head corresponding to the laser diode, and applying a forward bias to the laser diode; apply a first reverse bias to the laser diode during at least one intervening event; and transition from applying the first reverse bias to the at least one laser diode to applying the forward bias to the at least one laser diode.Type: GrantFiled: August 10, 2023Date of Patent: December 17, 2024Assignee: Western Digital Technologies, Inc.Inventors: Erhard Schreck, Sukumar Rajauria, Robert Smith
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Patent number: 12169634Abstract: A data storage device comprising a non-volatile storage medium configured to store data, a data port configured to receive and transmit data between a host computer system and the data storage device, and a controller. The controller is configured to receive, via the data port, a notification activation, and receive, via the data port, a command data structure comprising a command for the data storage device to perform an operation. The controller is further configured to in response to receiving the command data structure, perform the operation, the operation being defined by an in-progress state and a completed state, and in response to determining that the operation is in the completed state and in response to determining the notification activation, transmit, via the data port, a response data structure comprising an indication that the operation is in the completed state.Type: GrantFiled: June 29, 2022Date of Patent: December 17, 2024Assignee: Western Digital Technologies, Inc.Inventors: Eyal Hamo, Tomer Spector, Sagi Taragan
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Publication number: 20240411678Abstract: A data storage device and method are provided for predictable low-latency in a time-sensitive environment. In one embodiment, a data storage device is provided comprising a memory and a controller configured to communicate with the memory. The controller is further configured to: receive, from a host, an indication of a logical block address range that the host will later read; and in response to receiving the indication: read data from the logical block address range; and perform an action on the data to reduce a read latency when the host later reads the logical block address range. Other embodiments are disclosed.Type: ApplicationFiled: July 26, 2023Publication date: December 12, 2024Applicant: Western Digital Technologies, Inc.Inventors: Devika Nair, Amit Sharma
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Publication number: 20240412759Abstract: The present disclosure generally relates to spin-orbit torque (SOT) device comprising a bismuth antimony (BiSb) layer. The SOT device comprises a seed layer and a BiSb layer having a (012) orientation. The seed layer comprises at least one of an amorphous/nanocrystalline material with a nearest neighbor x-ray diffraction peak with a d-spacing in the range of about 2.02 ? to about 2.20 ?; a polycrystalline material having a (111) orientation and an a-axis of about 3.53 ? to about 3.81 ?; and a polycrystalline material having a cubic (100) or tetragonal (001) orientation and an a-axis of about 4.1 ? to about 4.7 ?. When the seed layer comprises an amorphous material or a polycrystalline material having a (111), the BiSb layer is doped, and the seed layer has a lower a/c ratio than when the seed layer comprises polycrystalline material having a cubic (100) or tetragonal (001) orientation.Type: ApplicationFiled: August 3, 2023Publication date: December 12, 2024Applicant: Western Digital Technologies, Inc.Inventors: Quang LE, Brian R. YORK, Cherngye HWANG, Xiaoyong LIU, Michael A. GRIBELYUK, Son T. LE, Hisashi TAKANO
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Publication number: 20240411688Abstract: In solid state memory devices, garbage collection can be a bottleneck in meeting stringent performance requirements of certain hosts that generate a relatively-large amount of data (e.g., hosts that generate video data). With such hosts, the performance drop caused by background garbage collection can result in video recording failures. The memory device and method presented herein performs background operations in such a way as to enhance sustained performance. In general, a counter is maintained that reflects an amount of memory written to by a host, as well as an amount of memory freed by garbage collection operations. Each step of a garbage collection operation can be performed in response to a value of the counter being greater than a threshold for the step such that there is a balance between memory written and memory freed.Type: ApplicationFiled: July 25, 2023Publication date: December 12, 2024Applicant: Western Digital Technologies, Inc.Inventors: Anamika Choudhary, Ramkumar Ramamurthy, Narendhiran Chinnaanangur Ravimohan, Lovish Singla, Meenakshi C, Bhagyashankar Muthu Kumaresan
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Publication number: 20240411476Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells disposed in memory holes connected to bit lines. The memory cells are configured to retain a threshold voltage corresponding to data states. The memory holes are grouped into a plurality of blocks. A control means is coupled to the bit lines and is configured to determine an amount of the memory cells of one of the plurality blocks that are programmed. The control means adjusts a bit line voltage based on the amount of the memory cells of the one of the plurality blocks that are programmed. The control means applies the adjusted bit line voltage to the plurality of bit lines while reading the memory cells to determine whether the memory cells have the threshold voltage above one or more of read levels associated with the data states in a read operation.Type: ApplicationFiled: August 3, 2023Publication date: December 12, 2024Applicant: Western Digital Technologies, Inc.Inventors: Albert Chen, Abu Naser Zainuddin, Xiang Yang, Jiahui Yuan
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Publication number: 20240412804Abstract: A non-volatile memory comprises a non-volatile memory structure that includes non-volatile memory cells. The non-volatile memory adjusts a ramp rate of a voltage signal applied to the non-volatile memory structure as part of a memory operation for the non-volatile memory cells. The adjusting the ramp rate is performed during the ramping up of the voltage signal and is based on voltage magnitude of the voltage signal at a particular time during the ramping up of the voltage signal.Type: ApplicationFiled: July 29, 2023Publication date: December 12, 2024Applicant: Western Digital Technologies, Inc.Inventors: Sai Gautham Thoppa, Parth Amin, Long Pham
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Publication number: 20240411684Abstract: A data storage device and method are provided for performing an action on an area of memory to satisfy a host-provided target operating condition. In one embodiment, a controller of the data storage device is configured to: receive, from a host, an identification of an area of the memory and a target operating condition for the area of the memory; monitor the area of the memory to determine whether the area of the memory satisfies the target operating condition; and in response to determining that the area of the memory does not satisfy the target operating condition, perform an action on the area of the memory to attempt to cause the area of the memory to satisfy the target operating condition. Other embodiments are provided, and each of the embodiments can be used alone or in combination.Type: ApplicationFiled: July 26, 2023Publication date: December 12, 2024Applicant: Western Digital Technologies, Inc.Inventors: Eyal Hamo, Sagi Taragan, Dvorah Freedman
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Publication number: 20240411636Abstract: A data storage device and method are disclosed for providing external-interrupt-based customized behavior. In one embodiment, a data storage device is provided comprising a memory and a controller configured to communicate with the memory. The controller is further configured to: receive an interrupt from a host indicating that a user is experiencing a performance problem with the data storage device; and in response to receiving the interrupt, take an action to address an issue in the data storage device that is causing the performance problem. Other embodiments are disclosed.Type: ApplicationFiled: July 28, 2023Publication date: December 12, 2024Applicant: Western Digital Technologies, Inc.Inventors: Lovish Singla, Shaheed Nehal A, Lovleen Arora
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Patent number: 12163921Abstract: Disclosed herein are detection methods that use magnetic nanoparticles (MNPs) to allow molecules to be identified. Embodiments of this disclosure include methods of using magnetic sensors (e.g., magnetoresistive sensors) to detect temperature-dependent magnetic fields (or changes in magnetic fields) emitted by MNPs, and, specifically to distinguish between the presence and absence of magnetic fields emitted, or not emitted, by MNPs at different temperatures selected to take advantage of knowledge of how the MNPs' magnetic properties change with temperature. Embodiments disclosed herein may be used for nucleic acid sequencing, such as deoxyribonucleic acid (DNA) sequencing.Type: GrantFiled: February 6, 2023Date of Patent: December 10, 2024Assignee: Western Digital Technologies, Inc.Inventors: Patrick Braganca, Daniel Bedau
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Patent number: 12165679Abstract: Disclosed herein is a magnetic storage device including a carriage with an opening. The opening defines a central axis and has multiple ridges parallel with the central axis. A cross-sectional shape of the opening, along a plane perpendicular to the central axis, includes multiple lobes, each terminating at two of the multiple ridges. The magnetic storage device also includes a pivot positioned in the opening in contact with the multiple ridges. The pivot has a cross-sectional shape, along the plane perpendicular to the central axis, that is circular. The carriage is rotatable, relative to at least one portion of the pivot, about the central axis.Type: GrantFiled: July 26, 2023Date of Patent: December 10, 2024Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yoshiya Usami, Koichi Suzuki, Michio Ueha, Takeshi Saito
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Patent number: 12165681Abstract: Methods, data storage devices, and computer-readable media for setting the flying height of a recording head are disclosed. A method may set a value of a control parameter of the recording head to force a predetermined location of the recording head to be a touchdown location. The method may involve incrementally moving the recording head toward a surface of a recording media, and, using a temperature sensor of the recording head, detecting an onset of touchdown at the touchdown location as the recording head is incrementally moving toward the surface of the recording media. The method may set the fly-height control power by backing off from an initial fly-height control power value, which may be a sum of a power level at which the onset of touchdown at the touchdown location was detected and a power corresponding to the value of the control parameter.Type: GrantFiled: September 15, 2023Date of Patent: December 10, 2024Assignee: Western Digital Technologies, Inc.Inventors: Qinghua Zeng, Jimmy Zhang, Sukumar Rajauria, Masaru Furukawa
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Patent number: 12164372Abstract: Aspects of a storage device including a memory and a controller are provided. The controller may determine to perform garbage collection on a superblock. During the garbage collection process, the controller will typically move the superblock into an erase pool for erasing the superblock. However, aspects of the disclosure are directed to a method of measuring a raw bit error rate (RBER) of the superblock prior to erasure. The measured RBER may be used to estimate a data retention time of the storage device and provide the customer with an early warning notification if a health metric of the storage devices reaches a threshold retention time.Type: GrantFiled: August 24, 2022Date of Patent: December 10, 2024Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Lisha Wang, Jinyoung Kim, Andrew Yu-Jen Wang, Jinghuan Chen, Kroum Stoev
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Publication number: 20240404607Abstract: Technology is disclosed herein for a dynamic bitscan. The dynamic bitscan may include performing a first bitscan of a first strict subset of memory cells. Then, based on results of the first bitscan, a determination is made whether to perform a second bitscan of a second strict subset of memory cells. Prior to the bitscan(s) a verify reference voltage may be applied to both strict subsets of memory cells. Skipping the second bitscan saves considerable time. However, the second bitscan is performed at least sometimes, which increases accuracy. The first strict subset of memory cells and the second strict subset of memory cells may have different locations relative to some point in the block that contains the memory cells. The first strict subset of memory cells and the second strict subset may have different programming speeds.Type: ApplicationFiled: July 27, 2023Publication date: December 5, 2024Applicant: Western Digital Technologies, Inc.Inventors: Yidan Liu, Liang Li, Chao Xu, Yingying Zhu
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Publication number: 20240403163Abstract: A plurality of control circuits are configured to individually connect to arrays that each include a plurality of non-volatile memory cells. Each non-volatile memory cell includes a programmable resistive element. Each control circuit is configured with an individual address offset. The plurality of control circuits are configured to: receive a read address from a memory controller in parallel, apply the respective individual address offsets to the read address to generate respective offset addresses, read portions of data from the respective offset addresses and send the data read from the offset addresses to the memory controller to perform Error Correction Code (ECC) decoding of the portions of data.Type: ApplicationFiled: July 27, 2023Publication date: December 5, 2024Applicant: Western Digital Technologies, Inc.Inventors: Dimitri Houssameddine, Kadriye Deniz Bozdag, Raj Ramanujan, Nicolas Irizarry
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Publication number: 20240404556Abstract: A data storage device may include a media comprising a magnetic recording layer and a heat-assisted magnetic recording (HAMR) head for writing to the magnetic recording layer, the HAMR head comprising: a waveguide, a main pole comprising a main-pole surface facing the magnetic recording layer, a near-field transducer (NFT) situated between the main pole and the waveguide, and a transparent overcoat. The NFT comprises a main body and a micropillar. The micropillar comprises a micropillar surface facing the magnetic recording layer. A first distance between the micropillar surface and the media is less than a second distance between the main-pole surface and the media. The transparent overcoat is situated on the main-pole surface and the micropillar surface.Type: ApplicationFiled: August 2, 2023Publication date: December 5, 2024Applicant: Western Digital Technologies, Inc.Inventors: Sukumar RAJAURIA, Erhard SCHRECK, Robert SMITH
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Publication number: 20240402927Abstract: In order to ensure that a bandwidth allocated to each tenant of a plurality of tenants of a data storage device is maintained, a controller of the data storage device may split a large read command, received from a host device, into a plurality of chunks, where each chunk corresponds to a distinct portion of the split large read command. Because the allocated bandwidth for a tenant is static, one or more chunks of the plurality of chunks, up to the allocated bandwidth, are executed, such that the bandwidth required to perform the one or more chunks does not exceed the allocated bandwidth for the particular tenant. Split information is added to the plurality of chunks in order to maintain coherency when executing the one or more chunks. Therefore, the agreed-upon allocated bandwidth for each tenant is maintained while performing large read commands requiring more bandwidth than allocated.Type: ApplicationFiled: July 6, 2023Publication date: December 5, 2024Applicant: Western Digital Technologies, Inc.Inventors: Elkana RICHTER, Shay BENISTY, Amir SEGEV
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Publication number: 20240404551Abstract: A HAMR data storage device may include a magnetic media and a slider comprising: a main pole, a waveguide, and a near-field transducer (NFT) situated between the main pole and the waveguide, wherein an air-bearing surface (ABS) of the slider comprises a transparent overcoat layer situated over the main pole, the waveguide, and the NFT, and wherein the transparent overcoat layer has a particular thickness such that, during an operational phase of the HAMR data storage device, a gap between a media-facing surface of the transparent overcoat layer and the magnetic media is less than about 0.5 nm.Type: ApplicationFiled: July 31, 2023Publication date: December 5, 2024Applicant: Western Digital Technologies, Inc.Inventors: Mehdi HABIBOLLAHZADEH, Sukumar RAJAURIA, Qing DAI, Sudha NARAYAN, Krisda SIANGCHAEW, Nattaporn KHAMNUALTHONG
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Publication number: 20240403178Abstract: In a word line leakage detection process in a NAND or other non-volatile memory device, a stress selected set of word lines have a high stress voltage applied while other parts of an array are biased to a low level. While stressing the memory array, the current drawn by the array is compared to a leakage detection current that increases in amplitude. For example, this can be done by mirroring the array current and comparing this with the current from a current source that increases in response to a digital input value and determining when it exceeds the mirror current, at which point the stress is discontinued. In addition to determining the amount of leakage, this approach results in low leakage word lines receiving less stress, while greater leakage result in greater amounts of stress being applied.Type: ApplicationFiled: July 3, 2023Publication date: December 5, 2024Applicant: Western Digital Technologies, Inc.Inventors: Troy Guan, Liang Li, Wendy Yu
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Publication number: 20240404608Abstract: A non-volatile memory is configured to transition memory cells from programmed data states with the higher ranges of threshold voltages to programmed data states with the lower ranges of threshold voltages without the transitioning the memory cells to the erased data state.Type: ApplicationFiled: July 29, 2023Publication date: December 5, 2024Applicant: Western Digital Technologies, Inc.Inventors: Liang Li, Ming Wang, Jiahui Yuan
