Abstract: Some areas (e.g., boundary wordlines) in a block of memory can be more error prone than others. Typically, errors in these areas are not detected until after the entire block is programmed. Handling such errors then can result in performance penalties and large data relocations. With the embodiments presented herein, a two-stage programming operation is provided. In the first stage, only the error-prone areas of the block are programmed, and a check is made to determine if an error occurred in that programming. In the second stage, the remaining portions of the block are programmed, but that only occurs after it is determined that the error-prone areas have been programmed successfully. Detecting and dealing with errors in the error-prone areas before the entire block is programmed avoid the performance penalties and large data relocations noted above.

Abstract: An apparatus is provided that includes a first pull-up driver circuit coupled to a first calibration node, an internal resistor circuit and first input/output pad on an integrated circuit die, a second pull-up driver circuit coupled to a second calibration node and second input/output pad on the integrated circuit die, a third pull-up driver circuit coupled to a third calibration node, a comparator including a first input terminal selectively coupled to the first calibration node, the second calibration node and the third calibration node, and a second input terminal coupled to a reference voltage, and circuitry configured to trim the reference voltage to compensate for a comparator offset, and trim an impedance of the internal resistor circuit by comparing a voltage on the first calibration node and the trimmed reference voltage. The trimmed impedance of the internal resistor circuit substantially equals a desired impedance of the third pull-up driver circuit.

Abstract: A data storage device and method are provided for using a dynamic floating flash region to secure a firmware update. In one embodiment, a data storage device is provided comprising a first non-volatile memory, a second non-volatile memory, and a controller. The controller is configured to communicate with the first and second non-volatile memories and further configured to: determine addresses in the second non-volatile memory to store portions of a firmware update, wherein the addresses are determined on-the-fly as opposed to being predetermined; and store the portion of the firmware update in the addresses in the second non-volatile memory. Other embodiments are provided.

Abstract: Technology is disclosed herein for a storage system that mitigates erase saturation when erasing memory cells. If erase does not pass after a number of erase loops, the storage system applies a program pulse to memory cells on faster to erase NAND strings. However, memory cells on slower to erase NAND strings are inhibited from programming. The program pulse increases the Vt of memory cells on the faster to erase NAND strings. Then, another erase loop is performed. The process may continue with additional loops, with each loop programming the memory cells on the faster to erase NAND strings followed by an erase pulse to all NAND strings and erase verify. Over-erase of the memory cells on the faster to erase NAND strings is therefore prevented. Moreover, slower to erase NAND strings that may otherwise be a bottleneck do not prevent successful completion of the erase.

Abstract: Rather than having unused die blocks, partial die blocks can contribute to a super block. In so doing, as much of the available physical capacity of the data storage device may be achieved. The result could be an increase in over provisioning (OP) and good capacity for the data storage device or an increase in die yield. An increase in good capacity through the use of previously unused physical blocks would lead to an increase in performance and endurance. A yield increase would result in a reduction in cost per die and per data storage device. A partial die block is the solution.

Abstract: The present disclosure generally relates to a magnetic recording device comprising a magnetic recording head. The magnetic recording device comprises a write head and a read head. The write head comprising a trailing shield, a main pole, and a leading shield, and the read head comprises a first shield, a second shield, and a magnetic sensor disposed between the first and second shields. In some embodiments, a shield is disposed between the leading shield and the first shield. A central axis of the write head is aligned with a central axis of the read head. The read head is spaced a distance of about 5 ?m to about 20 ?m from the write head such that the magnetic recording head is controllable to write data to a media using the write head and read verify the data using the read head.

Abstract: Various illustrative aspects are directed to a data storage device comprising a slider with a resistive temperature detector (RTD) having a first resistance electrically connected to a first amplifier and a plurality of controlled current sources and switches, and one or more processing devices configured to: control the switches to generate an alternating-bias signal having a first clock frequency for biasing the first resistance, modulate an input signal of the first amplifier using the first clock frequency to generate a modulated signal, demodulate an amplified modulated signal at an output of a second amplifier using the first clock frequency to generate a resistance detection signal, the second amplifier coupled to the first amplifier, and process the resistance detection signal to determine the first resistance and/or a change in value of the first resistance.

Abstract: A data storage device may include one or more disks, an actuator arm assembly comprising one or more disk heads, at least one laser diode positioned inside a corresponding laser diode cavity, a preamplifier, and one or more processing devices. The one or more processing devices are configured to: generate a reverse bias; apply, using the preamplifier, the reverse bias to the at least one laser diode to preheat a corresponding laser diode cavity to a target temperature prior to a write operation; control transition of the preamplifier from applying the reverse bias to applying a forward bias to the at least one laser diode; and activate the at least one laser diode to begin the write operation.

Abstract: The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. The plurality of word lines include a selected word line, a pair of neighboring word lines that are immediately adjacent the selected word line, and a plurality of non-neighboring word lines that are not immediately adjacent the selected word line. Circuitry can perform a sensing operation on at least one memory cell in the selected word line. During the sensing operation, the circuitry is configured to apply a reference voltage to the selected word line, apply different first and second pass voltages to the neighboring word lines, and apply a third pass voltage that is different than the first and second pass voltages to the plurality of non-neighboring word lines. The circuitry is further configured to sense a threshold voltage of the at least one memory cell.

Abstract: A storage device is communicatively coupled to a host that stores data on a primary memory package on the storage device. A controller on the storage device may monitor the temperature of components on the storage device and determine when the temperature exceeds a thermal temperature limit. When the temperature exceeds a thermal temperature limit, the controller may suspend certain operations on the primary memory package and write host data to the secondary memory package on the storage device. The controller may continue to monitor the temperature on the storage device, determine when the temperature on the storage device returns to an acceptable level, transfer data from the secondary memory package to the primary memory package, and resume writing host data to primary memory package.

Abstract: Performance on a storage device may be improved when executing a write command with sequential host data. The storage device optimizes logical-to-physical table updates for fixed granularity logical-to-physical tables that are populated when writing the sequential host data. A host interface module on the storage device may receive, from a host, a command to store the host data on a memory device and classify the host data as sequential host data or random host data. A flash translation layer on the storage device predetermines open contiguous blocks on the memory device where the sequential host data is to be written and provides a beginning address of the open contiguous blocks to the host interface module. The host interface module populates an address translation table with logical-to-physical mappings starting at the beginning address with an appropriate offset. Each entry in the address translation table corresponds to a fixed granularity.

Abstract: Improved automation can be achieved using command-parts. Rather than using a command to determine which key to use, command partitioning will generate a task-ID based on a key index table to determine what key to use. Based on the task-ID, an encryption engine (XTS) will know which key to use. The command is split into partitions with the same attributes. The amount of task-IDs created will equal the amount of partitions. Automation will be based on the task-IDs to create a completion for a host. The controller will then return to the key index table to count the completed commands and send the completion to the host.

Abstract: The present disclosure generally relates to a two dimensional magnetic recording (TDMR) spin-orbit torque (SOT) read head comprising bismuth antimony (BiSb) layers. The read head comprises a lower reader comprising a first SOT stack and an upper reader comprising a second SOT stack. The first SOT stack and the second SOT stack each individually comprise a BiSb layer recessed from a media facing surface (MFS) and a free layer exposed at the MFS. The BiSb layers of each SOT stack are recessed from the MFS a distance of about 5 nm to about 20 nm, the distance being less than a length of the free layers. In one embodiment, the lower reader and the upper reader share a current path. In another embodiment, the lower reader and the upper reader have separate current paths.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes and is configured to program the memory cells in a program operation. During the program operation, the control means programs the memory cells connected to at least one particular word line of the plurality of word lines using a first programming technique while programming the memory cells connected to plurality of word lines other than the at least one particular word line using a second programming technique different than the first programming technique.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes drain-side select gate transistors for coupling to a drain-side of memory holes of and configured to retain a transistor threshold voltage. The memory holes are arranged in rows comprising strings. The rows include semi-circle rows comprising the memory holes being partially cut by a slit half etch and full circle rows comprising the memory holes not cut. A control means is coupled to the drain-side select gate transistors of the memory holes and is configured to determine whether a downshift recovery trigger event has occurred in a plurality of memory operations. In response to determining the downshift recovery trigger event has occurred, the control means programs the transistor threshold voltage of the drain-side select gate transistors of the memory holes in at least one of the semi-circle rows to a target transistor threshold voltage.

Abstract: When copy commands are queued in a submission queue, there can potentially be many queued input-output (I/O) commands directed to the same logical range as the queued commands. This can result in data being invalidated immediately after it is written in memory, leading to write amplification and inefficient backend processing. To address this problem, the embodiments presented herein can be used to lock the range of logical block addresses of the queued commands, so that I/O commands are prevented from accessing the range of logical block addresses until the queued copy commands are completed.

Abstract: The memory device includes a chip with at least one voltage pump and a plurality of planes. The planes have arrays of memory cells that can be programmed and erased. At least some of the planes are at different distances from the at least one voltage pump. The memory device further includes control circuitry that is configured to program and erase the memory cells. The control circuitry is further configured to supply at least one voltage to a selected plane of the plurality of planes during a programming operation or an erase pulse and adjust the at least one voltage that is supplied to the selected plane by a parameter that is determined based on a distance between the selected plane and the at least one voltage pump.

Abstract: A data storage device can store data and parity information for the data in its memory. In some storage methodologies, data and parity information are striped across a plurality of memory dies (e.g., in a redundant array of independent drives (RAID) configuration). That way, if one of the memory dies fails, the data or the parity information can be reconstructed from the other memory dies. These embodiments recognize that because parity information is used relatively infrequently, the parity information can be stored in locations in the memory that have a relatively-worse performance than other areas of the memory. This can increase performance of the memory in situations where the parity information does not need to be read.

Abstract: During operation of a data storage device, a controller of the data storage device is configured to monitor a usage pattern of the data storage device based on commands sent by a host device. The usage pattern may reflect that the host device is primarily sending write commands or read commands. Because the host device is primarily sending one type of command, the controller may change an allocation of bandwidth/resources of the data storage device to better service the identified command type being sent by the host device. In other words, an increased amount of bandwidth/resources may be allocated to the operations/processes associated with the identified command type and the bandwidth/resources allocated to the non-identified command types may be decreased. Thus, more resources and bandwidth are dedicated to processing the identified command type.

Abstract: The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines and in a plurality of channels. The memory device also includes circuitry that is configured to conduct a hole pre-charge operation to inject holes into the plurality of channels. The hole pre-charge operation includes applying a first voltage to the plurality of word lines to make the plurality of memory cells conductive to holes and applying a voltage to the channels from one side of the memory block to inject holes into the channels.