Patents Assigned to Western Digital
  • Data storage device managing low endurance semiconductor memory write cache
    Patent number: 11893277
    Abstract: A data storage device is disclosed comprising a head actuated over a disk, a first semiconductor memory (SM) having a first endurance, and a second SM having a second endurance lower than the first endurance. A write command is received from a host including write data. When a size of the write command is less than a threshold, the write data is stored in a first SM write cache in the first SM, and when the size of the write command is greater than the threshold, the write data is stored in a second SM write cache in the second SM.
    Type: Grant
    Filed: February 20, 2021
    Date of Patent: February 6, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: David R. Hall
  • Dual performance trim for optimization of non-volatile memory performance, endurance, and reliability
    Patent number: 11894060
    Abstract: A non-volatile memory operates in a high perform mode when writing host data by using a first programming algorithm. When performing background operations, the non-volatile memory writes data using a lower performance, but higher endurance programming algorithm. In both cases the data is written in the same multi-level format, but the higher endurance programming algorithm uses, for example, a staircase waveform with a smaller step size. A count is kept for the number of program/erase cycles for memory blocks for both types of programming trim, but where a high performance write is weighted more heavily than a high endurance write.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: February 6, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: Ajay Shyam Manwani
  • Devices, systems, and methods of using smart fluids to control translocation speed through a nanopore
    Patent number: 11892445
    Abstract: Disclosed herein are devices, systems, and methods for controlling a translocation speed of a molecule through a nanopore. In some embodiments, a speed-control device comprises at least one fluid-retaining surface, a fluid region, a field-responsive fluid coupled to the fluid-retaining surface and situated in the fluid region. In some embodiments, a system comprises the nanopore, the speed-control device, and a field generator for generating a magnetic or electric field across the fluid region. The viscosity of the field-responsive fluid is dependent on a magnitude of the magnetic or electric field across the fluid region and can be controlled by changing a magnitude of the magnetic or electric field across the fluid region.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: February 6, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel Bedau, Justin P. Kinney
  • Heat-assisted magnetic recording (HAMR) head with main pole having narrow plasmonic recess
    Patent number: 11894018
    Abstract: A heat-assisted magnetic recording (HAMR) head has a slider with a gas-bearing-surface (GBS). The slider supports a near-field transducer (NFT) with an output tip at the GBS and a main magnetic pole that has a recess in the NFT-facing surface that contains plasmonic material. The plasmonic recess has a front edge at the GBS that has a cross-track width equal to or less than the cross-track width of the widest portion of the NFT output tip, and a back edge recessed from the GBS. A thermal shunt is located between the NFT and the main pole to allow heat to be transferred away from the optical spot generated by the NFT output tip, and is in contact with a region of the plasmonic recess near the back edge.
    Type: Grant
    Filed: August 20, 2022
    Date of Patent: February 6, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: Takuya Matsumoto
  • Execution condition embedded in a command or a request to storage device
    Patent number: 11893281
    Abstract: A storage device includes a non-volatile memory (NVM) and a storage device controller. The storage device controller includes a NVM interface coupled to the NVM and one or more task queues. The storage device controller is operable to pick a task from one or more queues of the storage device. The task is parsed based upon presence of an extra header segment with an execution condition. The task without the extra header segment is sent to execution. Whether the execution condition of the extra header segment of the task is met is determined. The task with the execution condition met is sent to execution. The task with the execution condition unmet is postponed.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: February 6, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Tomer Spector, Doron Ganon, Eran Arad
  • Content-Rich Error Notification
    Publication number: 20240036960
    Abstract: A data storage device includes a controller. The controller is coupled to a host device. The controller is configured to determine a quality of a peripheral component interconnect express (PCIe) link, wherein the quality of the PCIe link is either greater than or less than a threshold quality, and transmit an error notification to the host device via a sideband when the quality of the PCIe link is less than the threshold quality. The sideband is a different communication channel than the PCIe link. The error notification includes additional information regarding events occurring in the data storage device resulting in the quality of the PCIe link.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Kan Lip VUI, Judah Gamliel HAHN, Shay BENISTY
  • SYSTEM AND METHOD FOR DEPOSITING UNDERFILL MATERIAL
    Publication number: 20240038716
    Abstract: A method of dispensing an underfill material on a semiconductor device package. A substrate having a semiconductor chip electrically connected thereto and offset from the substrate by solder joints is provided. The semiconductor chip has a footprint defined by a length and width of the semiconductor chip. Standoff heights between the substrate and the semiconductor chip are calculated and used to determine a volume of underfill material needed to substantially fill a space between the substrate and the semiconductor chip. The determined volume of underfill material is dispensed on the substrate such that the space between the substrate and the semiconductor chip is substantially filled by the underfill material. The method may allow for improved dispensing an underfill material to substantially fill the space between the substrate and semiconductor chip when variations in standoff height are present.
    Type: Application
    Filed: July 26, 2022
    Publication date: February 1, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Choo Par Tan, Ee May Lim, Chee Ern NG
  • Storage System and Method for Optimizing Host-Activated Defragmentation and Proactive Garbage Collection Processes
    Publication number: 20240036764
    Abstract: A storage system is provided that performs a defragmentation operation or proactive garbage collection in its memory based on a command from a host. The command specifies which blocks in the memory should take part in the defragmentation operation by specifying a maximum amount of valid data that a block can have to qualify for defragmentation. That way, the storage system only performs defragmentation on those blocks that meet the validity criteria provided by the host. This can help improve performance of the storage system while reducing the degree of negative tradeoffs that may come with defragmentation or proactive garbage collection.
    Type: Application
    Filed: July 27, 2022
    Publication date: February 1, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Nadav Sober, Omer Katz
  • Voltage-controlled magnetic anisotropy memory device including an anisotropy-enhancing dust layer and methods for forming the same
    Patent number: 11889702
    Abstract: A magnetoelectric memory device includes a magnetic tunnel junction located between a first electrode and a second electrode. The magnetic tunnel junction includes a reference layer, a nonmagnetic tunnel barrier layer, a free layer, and a dielectric capping layer. At least one layer that provides voltage-controlled magnetic anisotropy is provided within the magnetic tunnel junction, which may include a pair of nonmagnetic metal dust layers located on, or within, the free layer, or a two-dimensional metal compound layer including a compound of a nonmagnetic metallic element and a nonmetallic element.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: January 30, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Alan Kalitsov, Derek Stewart, Bhagwati Prasad
  • Voltage-controlled magnetic anisotropy memory device including an anisotropy-enhancing dust layer and methods for forming the same
    Patent number: 11887640
    Abstract: A magnetoelectric memory device includes a magnetic tunnel junction located between a first electrode and a second electrode. The magnetic tunnel junction includes a reference layer, a nonmagnetic tunnel barrier layer, a free layer, and a dielectric capping layer. At least one layer that provides voltage-controlled magnetic anisotropy is provided within the magnetic tunnel junction, which may include a pair of nonmagnetic metal dust layers located on, or within, the free layer, or a two-dimensional metal compound layer including a compound of a nonmagnetic metallic element and a nonmetallic element.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: January 30, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Derek Stewart, Alan Kalitsov, Bhagwati Prasad
  • Thermal management of storage devices increasing host write performance
    Patent number: 11886260
    Abstract: Aspects of a storage device are thermal management of a non-volatile storage device are provided. In various embodiments, a storage device includes corresponding memory locations on two or more dies. Corresponding memory locations on each die form an addressable group. A controller in thermal communication with each of the dies may detect an excess temperature on one of the dies while performing sequential host writes. Upon such detection, the controller may disable all writes to the detected die while continuing to perform writes to the memory locations of the other dies without throttling the other dies. The controller may then reactivate writes to the detected die when the temperature drops below a threshold.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: January 30, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Sridhar Prudviraj Gunda, Kiran Kumar Eemani, Praveen Kumar Boda
  • Buffer Layers, Interlayers, and Barrier Layers Comprising Heusler Alloys for SOT Based Sensor, Memory, and Storage Devices
    Publication number: 20240032437
    Abstract: The present disclosure generally relates to spin-orbit torque (SOT) devices comprising a bismuth antimony (BiSb) layer. The SOT devices further comprises a nonmagnetic buffer layer, a nonmagnetic interlayer, a ferromagnetic layer, and a nonmagnetic barrier layer. One or more of the barrier layer, interlayer, and buffer layer comprise a polycrystalline non-Heusler alloy material, or a Heusler alloy and a material selected from the group consisting of: Cu, Ag, Ge, Mn, Ni, Co, Mo, W, Sn, B, and In. The Heusler alloy is a full Heusler alloy comprising X2YZ or a half Heusler alloy comprising XYZ, where X is one of: Mn, Fe, Co, Ni, Cu, Ru, Rh, Pd, Ag, Ir, Pt, and Au, Y is one of: Ti, V, Cr, Mn, Fe, Co, Ni, Zn, Y, Zr, Nb, Mo, Hf, and W, and Z is one of: B, Al, Si, Ga, Ge, As, In, Sn, Sb, and Bi.
    Type: Application
    Filed: May 15, 2023
    Publication date: January 25, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Quang LE, Brian R. YORK, Cherngye HWANG, Xiaoyong LIU, Susumu OKAMURA, Michael A. GRIBELYUK, Xiaoyu XU, Randy G. SIMMONS, Kuok San HO, Hisashi TAKANO
  • Accelerated Encryption During Power Loss
    Publication number: 20240028524
    Abstract: The present disclosure generally relates to a XTS cache operation during a power down event. Upon detection of power loss, data that is waiting to be encrypted needs to be flushed to the memory device. For any unaligned data or data less than a flash management unit (FMU) size, the data is grouped together and, if necessary, padded to reach the FMU size and then encrypted, merged with other data FMUs, and written to the memory device. Grouping the unaligned data reduces the amount of padding necessary to reach FMU size and also reduces the amount of data to be encrypted. As such, data flushing can be accomplished using the limited amount of remaining power during the power loss event.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 25, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SEGEV, Shay BENISTY
  • Dual spindle motor hard disk drive
    Patent number: 11881232
    Abstract: A dual disk spindle motor hard disk drive includes a first portion having a first spindle motor and a first disk media stack mounted thereon and housed in a first enclosure, and a second portion having a coaxial second spindle motor and a second disk media stack mounted thereon and housed in a second enclosure, where the second portion further includes both the first actuator and head sliders corresponding to the first disk stack as well as the second actuator and head sliders corresponding to the second disk stack. The first and second portions are coupled together such that the open sides of the enclosures mate, referred to herein as a clamshell configuration, and each separate spindle motor is configured to operate independently of the other. With independent control of multiple spindle motors, various control functions may be utilized to address power consumption and temperature control.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: January 23, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Nan-Hsun Han, Brian K. Lee, Danny J. Kastler
  • Method and device for covertly communicating state changes
    Patent number: 11882434
    Abstract: Disclosed herein is a device configured to covertly communicate state information within a transmitter address field of a message. The device comprises a memory configured to store a state key and state information of the device, and a controller in communication with the memory. The controller is configured to apply a one-way function, using the state key, to the state information to produce a transmitter address, and transmit the message, including the transmitter address in the transmitter address field of the message.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: January 23, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Brian Edward Mastenbrook, David Robert Arnold
  • Data storage device and method for energy feedback and report generation
    Patent number: 11880256
    Abstract: A data storage device and method for energy feedback and report generation are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to maintain an association between logical addresses and application identifiers of applications on a host; determine power implications associated with a command to access a logical address of the memory; generate a report on the power implications, wherein the report identifies an application identifier associated with the logical address; and provide the report to the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: January 23, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: Ramanathan Muthiah
  • Spin torque oscillator with enhanced spin polarizer
    Patent number: 11881236
    Abstract: The present disclosure generally relates to a magnetic recording head comprising a spintronic device. The spintronic device is disposed between a main pole and a trailing shield of the magnetic recording head. The spintronic device comprises a multilayer spacer layer comprising a Cu layer in contact with a spin torque layer and a spin transparent texture layer disposed on the Cu layer, the spin transparent texture layer comprising AgSn or AgZn. A multilayer notch comprising a CoFe layer is disposed over the spin transparent texture layer of the multilayer spacer layer and a Heusler alloy layer is disposed on the CoFe layer, the Heusler alloy layer comprising CoMnGe, CoFeGe, or CoFeMnGe. The multilayer spacer layer and the multilayer notch result in the spintronic device having a high spin polarization and a reduced critical current.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: January 23, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: James Mac Freitag, Susumu Okamura, Christian Kaiser
  • Storage system and method for preserving overwritten data to allow a future rollback
    Patent number: 11880603
    Abstract: A storage system receives a command from a host to overwrite data that is stored in a memory of the storage system. The command may have been issued in error or by malware, so the storage system preserves the data that the host wants to overwrite, just in case the host later wants to recover the data. To do this, the storage system associates the physical address of the location of the memory that stores the data with a logical block address that is inaccessible by the host. To recover the data, the storage system replaces the logical block address that is inaccessible by the host with a logical block address that is accessible by the host.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: January 23, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Nicholas Thomas, Eran Erez, Matt Davidson
  • Sector mapout of low coercivity media for enhancing aerial density
    Patent number: 11881238
    Abstract: Various illustrative aspects are directed to a data storage device comprising one or more disks, an actuator assembly comprising one or more disk heads; and one or more processing devices, configured to detect a plurality of areas with a coercivity lower than a threshold on the one or more disks; map out one or more sectors in each of the plurality of lower coercivity areas on the one or more disks; write data to, or read data from, the one or more disks, based at least in part on mapping out the one or more sectors in each of the plurality of lower coercivity areas. In some embodiments, the writing or reading data comprises writing data to, or reading data from, one or more sectors of the one or more disks that are not mapped out.
    Type: Grant
    Filed: August 3, 2022
    Date of Patent: January 23, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Zarko Popov, Wayne H. Vinson, Xing Huo, Mao Nishiyama
  • Optical devices for tilt in camera systems
    Patent number: 11882361
    Abstract: Aspects of the present disclosure generally relate to optical devices and related methods that facilitate tilt in camera systems, such as tilt of a lens. In one example, an optical device includes a lens, an image sensor disposed below the lens, a plurality of magnets disposed about the lens, and a plurality of: (1) vertical coil structures coiled in one or more vertical planes and (2) horizontal coil structures coiled in one or more horizontal planes. When power is applied, the coil structures can generate magnetic fields that, in the presence of the magnets, cause relative movement of the coil structures and associated structures. The plurality of vertical coil structures are configured to horizontally move the lens. The plurality of horizontal coil structures are configured to tilt the lens when differing electrical power is applied to at least two of the plurality of horizontal coil structures.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: January 23, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Quang Le, Rajeev Nagabhirava, Kuok San Ho, Zhigang Bai, Zhanjie Li, Xiaoyong Liu, Daniele Mauri