Abstract: An improved pseudomorphic high electron mobility transistor (pHEMT) and heterojunction bipolar transistor (HBT) integrated epitaxial structure and the fabrication method thereof, in which the structure comprises a substrate, a pHEMT structure, an etching-stop spacer layer, and an HBT structure. The pHEMT's structure comprises a buffer layer, a barrier layer, a first channel spacer layer, a channel layer, a second channel spacer layer, a Schottky barrier layer, an etching-stop layer, and at least one cap layer. The fabrication method of an HBT and a pHEMT are also included.

Abstract: An improved structure of backside copper metallization for semiconductor devices and a fabrication method thereof, in which the improved structure comprises sequentially from top to bottom an active layer, a substrate, a backside metal seed layer, at least one thermal expansion buffer layer, a backside metal layer, and at least one oxidation resistant layer, in which the backside metal seed layer is formed of Pd, and the thermal expansion coefficient of the thermal expansion buffer layer is in the range between the thermal expansion coefficients of the backside metal seed layer and of the backside metal layer. The semiconductor chip using the structure provided by the present invention can sustain high-temperature operations.

Abstract: A group III nitride-based high electron mobility transistor (HEMT) is disclosed. The group III nitride-based high electron mobility transistor (HEMT) comprises sequentially a substrate, a GaN buffer layer, a GaN channel layer, a AlN spacer layer, a barrier layer, a GaN cap layer, and a delta doped layer inserted between the AlN spacer layer and the barrier layer. The HEMT structure of the present invention can improve the electron mobility and concentration of the two-dimensional electron gas, while keeping a low contact resistance.

Abstract: A method of processing copper backside metal layer for semiconductor chips is disclosed. The backside of a semiconductor wafer, with electronic devices already fabricated on the front side, is first coated with a thin metal seed layer by either electroless plating or sputtering. Then, the copper backside metal layer is coated on the metal seed layer. The metal seed layer not only increases the adhesion between the front side metal layer and the copper backside metal layer through backside via holes, but also prevents metal peeling from semiconductor's substrate after subsequent fabrication processes, which is helpful for increasing the reliability of device performances. Suitable materials for the metal seed layer includes Pd, Au, Ni, Ag, Co, Cr, Pt, or their alloys, such as NiP, NiB, AuSn, Pt—Rh and the likes. The use of Pd as seed layer is particularly useful for the copper backside metal layer, because the Pd layer also acts as a diffusion barrier to prevent Cu atoms entering the semiconductor wafer.

Abstract: The present invention relates to a compound semiconductor integrated circuit with three-dimensionally formed components, such as three-dimensionally formed bond pads or inductors, positioned above an electronic device. The dielectric layer inserted between the electronic device and the bond pads or inductors thereon has a thickness between 10 to 30 microns, so that it can effectively mitigate the effect of the structure on the device performance. A protection layer can be disposed to cover the electronic devices to prevent contamination from the bond pad or inductor material to the electronic device, and therefore the lower cost copper can be used as the bond pad and inductor material. The three-dimensional bond pad can be used in wire bonding or bump bonding technology.

Abstract: A method for mounting a thinned semiconductor wafer on a carrier substrate for further processing is disclosed. The method consists of a series of steps, which is based on providing a frame with a double-side tape to mount the thinned wafer on the carrier substrate. The frame is used to support the double-side tape and can be designed to fit the conventional production line for holding, picking and transferring wafers. The carrier substrate can be a sapphire substrate, a quartz substrate or other substrates that can sustain further processing, such as thermal treatments and/or chemical etchings. The method of the present invention not only prevents possible damages to the highly brittle chip after wafer thinning, but also fits the conventional production line for processing semiconductor wafers.

Abstract: A method of backside metal process for semiconductor electronic devices, particularly of using an electroless plating for depositing a metal seed layer for the plated backside metal film. The backside of a semiconductor wafer, with electronic devices already fabricated on the front side, is first coated with a thin metal seed layer by electroless plating. Then, the backside metal layer, such as a gold layer or a copper layer, is coated on the metal seed layer. The metal seed layer not only increases the adhesion between the front side metal layer and the backside metal layer through backside via holes, but also prevents metal peeling after subsequent fabrication processes. This is helpful for increasing the reliability of device performances. Suitable materials for the metal seed layer includes Pd, Au, Ni, Ag, Co, Cr, Cu, Pt, or their alloys, such as NiP, NiB, AuSn, Pt—Rh and the likes.

Abstract: A method of backside metal process for semiconductor electronic devices, particularly of using an electroless plating for depositing a metal seed layer for the plated backside metal film. The backside of a semiconductor wafer, with electronic devices already fabricated on the front side, is first coated with a thin metal seed layer by electroless plating. Then, the backside metal layer, such as a gold layer or a copper layer, is coated on the metal seed layer. The metal seed layer not only increases the adhesion between the front side metal layer and the backside metal layer through backside via holes, but also prevents metal peeling after subsequent fabrication processes. This is helpful for increasing the reliability of device performances. Suitable materials for the metal seed layer includes Pd, Au, Ni, Ag, Co, Cr, Cu, Pt, or their alloys, such as NiP, NiB, AuSn, Pt—Rh and the likes.

Abstract: A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is used to obtain a better coverage on the surface for facilitating gate metal lift-off. The dual-resist method not only reduces the final gate length, but also mitigates the gate recess undercuts, as compared with those fabricated by the conventional single-resist processes. Furthermore, the dual-resist method of the present invention is also beneficial for the fabrication of multi-gate device with good gate-length uniformity.

Abstract: A full periphery multi-gate transistor with ohmic strip is disclosed. The multi-gate transistor comprises a substrate, a multi-layer structure, a source finger, a drain finger, and a gate. The gate is formed between the source finger and the drain finger, and then a conduction channel is formed between the source finger and the drain finger. The gate also meanderingly wraps around an end of the source finger and an end of the drain finger. Therefore, the end of the source finger and the end of the drain finger are parts of the conduction channel and both provide channel conductance. In addition, an ohmic strip is formed between two gate lines of the gate.

Abstract: An on-chip circuit for protection against electrostatic discharge (ESD) is disclosed. Unlike conventional ESD protection circuit using high turn-on voltage diode string, the circuit uses a plural of enhancement-mode HEMT/MESFET triggered by a shorter diode string to shunt large ESD current for protected susceptive RF circuit. Further, by using dual-gate technology of enhancement-mode HEMT/MESFET, the on-chip ESD protection circuit has the less parasitic capacitance without expanding device size for vulnerable RF circuit.

Abstract: A method for mounting a thinned semiconductor wafer on a carrier substrate for further processing is disclosed. The method consists of a series of steps, which is based on providing a frame with a double-side tape to mount the thinned wafer on the carrier substrate. The frame is used to support the double-side tape and can be designed to fit the conventional production line for holding, picking and transferring wafers. The carrier substrate can be a sapphire substrate, a quartz substrate or other substrates that can sustain further processing, such as thermal treatments and/or chemical etchings. The method of the present invention not only prevents possible damages to the highly brittle chip after wafer thinning, but also fits the conventional production line for processing semiconductor wafers.

Abstract: A high linearity doped-channel FET, comprises a substrate, a buffer layer, a channel layer and a cap layer stacked downwardly thereon. The cap layer has a source region, a drain region with a distance apart from the source region and a gate region formed by removing part of the cap layer between the source region and the drain region. A source electrode and a drain electrode are respectively formed on the source region and the drain region, and a gate electrode is formed on the gate region, wherein the source region and the drain region of the cap layer are respectively provided with an opening for forming a good ohmic contact between the source region and the drain region with the channel layer respectively.

Abstract: A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is used to obtain a better coverage on the surface for facilitating gate metal lift-off. The dual-resist method not only reduces the final gate length, but also mitigates the gate recess undercuts, as compared with those fabricated by the conventional single-resist processes. Furthermore, the dual-resist method of the present invention is also beneficial for the fabrication of multi-gate device with good gate-length uniformity.

Abstract: A two-port dual-gate field-effect transistor for amplifier applications, wherein a self-bias circuit includes a number of passive elements, such as resistors, diodes and capacitors, is utilized to coupled the output of the amplifier with a second gate of the dual-gate device as a bias source, which transforms the conventional three-port cascade topology into a two-port dual-gate device so as to facilitate device testing, modeling, and packaging for discrete device application. The technology improves the RF performance in conventional two-port single-gate HEMT devices, with slight noise figure degradation.

Abstract: A two-port dual-gate field-effect transistor for amplifier applications, wherein a self-bias circuit comprising a number of passive elements, such as resistors, diodes and capacitors, is utilized to coupled the output of the amplifier with a second gate of the dual-gate device as a bias source, which transforms the conventional three-port cascode topology into a two-port dual-gate device so as to facilitate device testing, modeling, and packaging for discrete device application. The technology is for improving the RF performance of conventional two-port single-gate HEMT device, with slightly noise figure degradation. This innovation doesn't require complicated RF testing and modeling as compared with conventional dual-gate devices. The two-port dual-gate device fits packaging molds of conventional two-port discrete device, hence the production line thereof can be easily extended to low noise amplifier and power amplifier applications.

Abstract: An epitaxial layers structure and a method for fabricating HBTs and HEMTs on a common substrate are disclosed. The epitaxial layers comprise generally a set of HBT layers on the top of a set of HEMT layers. The method can be used to fabricate HBT, E-mode HEMT and D-mode HEMT as well as passive devices, that enabling monolithic integration of a significant number of devices on a common substrate by a cost-effective way.

Abstract: A thin wafer carrying device includes a laminated board made of layers of compound material so that the thin wafer is put on the circular board. The compound material includes reinforcement material and high-polymer resin. A metal film good in electric conductivity is coated to the compound material. The compound material has been used in printed circuit boards. The carrying device includes a plurality of tiny holes and a vacuum system located beneath the circular board. The thin wafer is attracted on the carrying device by the method of vacuum and is convenient to be tested, processed and transported.

Abstract: A heterojunction bipolar transistor (HBT) power transistor with improved ruggedness is disclosed. The optimized design of HBT power transistor combines the use of ballasting resistors, coupling capacitors, as well as novel layout of the transistor cell, which avoids the problem of thermal runaway while maintaining the performance of the HBT power transistor.