Abstract: A power amplifier (PA) has been disclosed for linearity improvement. The PA comprises at least an amplifying transistor and at least an auxiliary transistor. Each amplifying transistor of the at least an amplifying transistor includes a first terminal for receiving an input signal of the PA, a second terminal for delivering an output signal of the PA, and a third terminal. Each auxiliary transistor of the at least an auxiliary transistor includes a first terminal, a second terminal coupled to the second terminal of the at least an amplifying transistor, and a third terminal electrically connected to the first terminal of the at least an amplifying transistor.

Abstract: A high-frequency package comprises a die; a plurality of leads; and a die pad; wherein a surface of the die pad is lower than top surfaces of the plurality of leads, the die is disposed on the die pad with the lower surface, such that a top surface of the die is substantially aligned with the top surfaces of the plurality of leads.

Abstract: An integrated structure of power amplifier and acoustic wave device comprises: a compound semiconductor epitaxial substrate, a power amplifier upper structure formed on a first side of said compound semiconductor epitaxial substrate, and a film bulk acoustic resonator formed on a second side of said compound semiconductor epitaxial substrate; wherein forming an epitaxial structure on a compound semiconductor substrate to form said compound semiconductor epitaxial substrate; wherein said first side of said compound semiconductor epitaxial substrate and said power amplifier upper structure form a power amplifier; said second side of said compound semiconductor epitaxial substrate and said film bulk acoustic resonator form an acoustic wave device; the integrated structure of power amplifier and acoustic wave device on the same compound semiconductor epitaxial substrate is capable of reducing the component size, optimizing the impedance matching, and reducing the signal loss between power amplifier and acoustic w

Abstract: A low noise amplifier (LNA) has been disclosed for the noise and linearity performance improvement. The LNA includes an amplifying transistor and an auxiliary transistor. The amplifying transistor includes a first terminal for receiving an input signal of the LNA, a second terminal for outputting an output signal of the LNA, and a third terminal. The auxiliary transistor has a first terminal, a second terminal coupled to the second terminal of the amplifying transistor, and a third terminal electrically connected to the first terminal of the amplifying transistor.

Abstract: An improved structure of backside copper metallization for semiconductor devices and a fabrication method thereof, wherein the improved structure comprises sequentially from top to bottom an active layer, a substrate, a backside metal seed layer, a high-temperature sustaining buffer layer, a backside metal layer and at least one oxidation resistant layer, wherein the backside metal seed layer contains Pd and P, the high-temperature sustaining buffer layer is made of Ni, Ag or Ni alloys, and the backside metal layer is made of Cu. The semiconductor chip using the structure provided by the present invention can sustain high-temperature operations.

Abstract: A high-frequency package comprises a ground lead, connected to a die, occupying a side of the high-frequency package, wherein a slot is formed within the ground lead; and a signal lead, connected to the die, disposed within the slot; wherein the ground lead surrounds the signal lead, and the ground lead and the signal lead form as a ground-signal-ground structure.

Abstract: An integrated structure of power amplifier and acoustic wave device comprises: a compound semiconductor epitaxial substrate, a power amplifier upper structure formed on a first side of said compound semiconductor epitaxial substrate, and a film bulk acoustic resonator formed on a second side of said compound semiconductor epitaxial substrate; wherein forming an epitaxial structure on a compound semiconductor substrate to form said compound semiconductor epitaxial substrate; wherein said first side of said compound semiconductor epitaxial substrate and said power amplifier upper structure form a power amplifier; said second side of said compound semiconductor epitaxial substrate and said film bulk acoustic resonator form an acoustic wave device; the integrated structure of power amplifier and acoustic wave device on the same compound semiconductor epitaxial substrate is capable of reducing the component size, optimizing the impedance matching, and reducing the signal loss between power amplifier and acoustic w

Abstract: A layout structure of HBTs comprising one or more HBTs, each of which comprises a base electrode, an emitter electrode, and a collector electrode. A passive layer, a first dielectric layer, a collector redistribution layers, one or more emitter copper pillars, and one or more collector copper pillars are formed above the one or more HBTs. The passive layer comprises a collector and an emitter pads. The first dielectric layer has one or more emitter and collector via holes. The emitter copper pillar is disposed on the emitter via hole and forms an electrical connection to the emitter electrode. The collector copper pillar is disposed on the collector redistribution layer and forms electrical connection to the collector electrode. The layout design of the emitter and collector copper pillars is therefore flexible, and the heat dissipation efficiency is improved.

Abstract: A fabrication method for dicing semiconductor wafers using laser cutting techniques, which can effectively prevent the devices on semiconductor die units from the phenomenon of etching undercut caused by the sequential steps after laser cutting, comprises following steps: covering the wafer surface with a protection layer; dicing the wafer by laser and separating the die units from each other; removing the laser cutting residues on the devices on the die units via wet etching by an acidic water solution; removing the protection layer by a non-acidic water solution and cleaning the devices on the die units. The selection of materials for the protection layer must consider the following factors: where (1) the materials for the protection layer must have relatively good properties for adhering and covering on the wafer; (2) the materials for the protection layer must be corrosion-resistant to the acidic water solution for etching residues.

Abstract: A structure of a semiconductor chip with substrate via holes and metal bumps and a fabrication method thereof. The structure comprises a substrate, at least one backside metal layer, at least one first metal layer, at least one electronic device, and at least one metal bump. The substrate has at least one substrate via hole penetrating through the substrate. The at least one first metal layer and electronic device are formed on the front side of the substrate. The at least one metal bump is formed on the at least one first metal layer. The at least one backside metal layer is formed on the backside of the substrate covering the inner surface of the substrate via hole and at least part of the backside of the substrate and connected to the first metal layer on the top of the substrate via hole.

Abstract: A high breakdown voltage metal-insulator-metal capacitor for compound semiconductor integrated circuit comprises a substrate, an isolation layer, a first metal layer, a dielectric layer, an adhesion layer and a second metal layer. The dielectric layer is formed by alternately stacking plural HfO2 layers and plural SiO2 layers. The thickness of each layer of the plural HfO2 layers is between 30 ? to 100 ? so as to reduce the leakage current, enhance the breakdown voltage and increase the capacitance density of each layer of the plural HfO2 layers. And the total thickness of the dielectric layer is thicker than 500 ? such that the breakdown voltage of the capacitor is higher than 50 V.

Abstract: A method to produce high electron mobility transistors with Boron implanted isolation comprises the following steps: on a substrate forming in sequence a nucleation layer, a buffer layer, a barrier layer and a cap layer; coating a photoresist layer on the cap layer; photomasking and by exposure eliminating the photoresist layer of at least one isolation region; executing plural times an ion implantation process including: adjusting an incident angle of a Boron ion beam with respect to the substrate, and implanting the Boron ion beam into the cap layer, the barrier layer, the buffer layer, the nucleation layer and the substrate within the at least one isolation region so as to form an isolation structure while rotating the substrate by a rotation angle; eliminating the rest of the photoresist layer by exposure; and forming a source, a drain and a gate on the cap layer.

Abstract: A compound semiconductor integrated circuit is provided, comprising a substrate, at least one compound semiconductor electronic device, a first metal layer, a protection layer, a plurality of second metal layers, and at least one dielectric layer. The first metal layer contains Au but does not contain Cu, and is at least partly electrically connected to the compound semiconductor electronic device. The protection layer covers the compound semiconductor electronic device and at least part of the first metal layer. Each of the plurality of second metal layers contains at least a Cu layer, and at least one of the plurality of second metal layers is partly electrically connected to the first metal layer described above. The at least one dielectric layer separates each pair of adjacent second metal layers. The second metal layers are used to form passive electronic components.

Abstract: An integrated circuit with ESD protection comprises at least one ESD protection circuit block, which comprises a DC blocking capacitor connected in parallel with at least one compound semiconductor enhancement mode FET as an ESD protection device. The ESD protection circuit block that is built in an integrated circuit provides ESD protection while minimizing the generation of unwanted nonlinear signals resulting from the ESD protection. An integrated circuit comprises a high frequency circuit, a switching element, and two ESD protection circuit blocks, in which the high frequency circuit is connected between a first terminal and a second terminal for inputting or outputting the RF signals, the first ESD protection circuit block is connected from a branch node between the first terminal and the high frequency circuit to the switching element, and the second ESD protection circuit block is connected from the switching element to the ground.

Abstract: An integrated structure of compound semiconductor devices is disclosed. The integrated structure comprises from bottom to top a substrate, a first epitaxial layer, an etching-stop layer, a second epitaxial layer, a sub-collector layer, a collector layer, a base layer, and an emitter layer, in which the first epitaxial layer is a p-type doped layer, the second epitaxial layer is an n-type graded doping layer with a gradually increased or decreased doping concentration, and the sub-collector layer is an n-type doped layer. The integrated structure can be used to form an HBT, a varactor, or an MESFET.

Abstract: A method for forming a through wafer via hole in a semiconductor device, wherein the semiconductor device comprises a wafer having a SiC substrate with a front side and a backside, a GaN-based layer formed on the front side of the SiC substrate, and a mask structure formed on the backside of the SiC substrate defining an etching area. The etching area is first descummed A through substrate via hole is formed by etching the etching area through the SiC substrate. The mask structure is removed and the inner surface of the through substrate via hole is cleaned. The inner surface of the through substrate via hole is then descummed A through wafer via hole is formed by etching through the GaN layer in the through substrate via hole. And lastly the inner surface of the through wafer via hole is cleaned.

Abstract: A wafer holding structure for wafer backside processing, in which the wafer comprises a SiC substrate and a semiconductor device layer. The SiC substrate has a back surface and a front surface, and the semiconductor device layer has a first surface and a second surface. The semiconductor device layer is disposed on the SiC substrate with its first surface in contact with the front surface of the SiC substrate. The wafer holding structure comprises a wafer carrier and an adhesive coating. The wafer carrier is made of n-type conductive SiC, and has a thermal expansion coefficient that is well matched to the SiC substrate. The wafer carrier is mounted to the second surface of the semiconductor device layer and the adhesive coating is coated between the wafer carrier and the second surface of the semiconductor device layer.

Abstract: An improved structure of heterojunction field effect transistor (HFET) and a fabrication method thereof are disclosed. The improved HFET structure comprises sequentially a substrate, a channel layer, a spacing layer, a carrier supply layer, a Schottky layer, a Schottky capping layer formed by a higher energy gap material, a tunneling layer formed by a lower energy gap material, a first etching stop layer, and a first n type doped layer.

Abstract: The present invention relates to compound semiconductor ESD protection devices of three types. The device comprises a multi-gate enhancement mode PET (E-PET). For the type I compound semiconductor ESD protection device, the source electrode is connected to the plural gate electrodes through at least one first resistor, and the drain electrode is connected to the plural gate electrodes through at least one second resistor. For the type II compound semiconductor ESD protection device, at least one of the plural gate electrodes are connected to at least one of the inter-gate regions between two adjacent gate electrodes through at least one fourth resistor. For the type compound semiconductor ESD protection device, the plural gate electrodes are connected to the source or drain electrodes through at least one seventh resistor. Any two gate electrodes in the three types of compound semiconductor ESD protection devices can be connected by a resistor.

Abstract: A multi-gate semiconductor device with inter-gate conductive regions being connected to balance resistors is provided. The multi-gate semiconductor device comprises a substrate, a multilayer structure formed upon the substrate, a first ohmic electrode, a second ohmic electrode, a plural of gate electrodes, at least one conductive region, and at least one resistive component. When put into practice, the multi-gate semiconductor device is advantageous in reducing the voltage drop along the conductive region with a minimal change in device layout, improving the OFF-state linearity while retaining a low insertion loss, and minimizing the area occupied by the resistor and hence the total chip size.