Abstract: A chip stack having a protection structure for semiconductor device package comprises a first chip and a second chip stacked with each other. A first surface of the first chip and a second surface of the second chip are facing to each other. At least one metal pillar is formed on at least one of the first surface and the second surface and connected with the other. At least one protection ring is formed on at least one of the first surface and the second surface and having a first gap with the other. At least one electrical device is formed on at least one of the first surface and the second surface and is located inside at least one of the at least one protection ring, wherein the at least one electrical device includes a temperature sensor.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate; a winding structure formed on a top side the semiconductor substrate, wherein the winding structure comprises one or more metal lines winding with respect to a center of the winding structure; and a backside metal formed under a backside of the semiconductor substrate; wherein a hollow slot is formed within the backside metal, and a projection of the winding structure is within the hollow slot.

Abstract: A HBT on a GaAs substrate is presented, wherein its base comprises a first base layer comprising IniGa1-iAs with an Indium content i with a slope s1 and a second base layer on the emitter side comprising InjGa1-jAs with an Indium content j with a slope s2, and an average of s1 is half of the average of s2 or smaller; or the base comprises a first base layer comprising InmGa1-mAs with an Indium content m and a second base layer on the emitter side comprising InnGa1-nAs with an Indium content n, and an average of n is larger than the m at a second base layer side; or the base comprises a first base layer pseudomorphic to GaAs with a bulk lattice constant larger than GaAs, and the emitter comprises a first emitter layer pseudomorphic to GaAs with a bulk lattice constant smaller than GaAs.

Abstract: A bulk acoustic wave resonator with a mass adjustment structure comprises a supporting layer, a lower metal layer, a piezoelectric layer, an upper metal layer and a mass adjustment structure. The supporting layer is formed on a substrate. The supporting layer has a cavity, and the cavity has a top-inner surface. The lower metal layer is formed on the supporting layer. The piezoelectric layer is formed on the lower metal layer. The upper metal layer is formed on the piezoelectric layer. An acoustic wave resonance region is defined by an overlapping region of projections of the upper metal layer, the piezoelectric layer, the lower metal layer, the supporting layer and the cavity. The acoustic wave resonance region is divided into a peripheral region and a central region. The mass adjustment structure comprises a peripheral mass adjustment structure formed on the top-inner surface within the peripheral region.

Abstract: An InGaAlP Schottky field effect transistor with stepped bandgap ohmic contact, comprising: a buffer layer, a channel layer, a carrier supply layer, a Schottky barrier layer, an intermediate bandgap layer, a cap layer and an ohmic metal layer sequentially formed on a compound semiconductor substrate; wherein the Schottky barrier layer is made of InGaAlP; the ohmic metal layer and the cap layer form an ohmic contact. The Schottky barrier layer, the intermediate bandgap layer and the cap layer have a Schottky-barrier-layer bandgap, an intermediate bandgap and a cap-layer bandgap respectively, wherein the intermediate bandgap is less than the Schottky-barrier-layer bandgap and greater than the cap-layer bandgap.

Abstract: An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer, at least one stress balance layer and a die attachment layer. The contact metal layer is formed on a bottom surface of a compound semiconductor wafer; the at least one stress balance layer is formed on a bottom surface of the contact metal layer, wherein the at least one stress balance layer is made of at least one conductive material; the die attachment layer is formed on a bottom surface of the at least one stress balance layer, wherein the die attachment layer is made of conductive material. By locating the at least one stress balance layer between the contact metal layer and the die attachment layer, the stress suffered by the compound semiconductor wafer is balanced so that the distortion of the compound semiconductor wafer is reduced.

Abstract: A thermal sensor circuit comprises a conversion circuit which is one of a buck DC-DC converter circuit and a boost DC-DC converter circuit, wherein the conversion circuit comprises an inductor and an output terminal. A thermal sensor senses a thermal variation correlated to a capacitance variation of the thermal sensor. The capacitance variation induces an internal parasitic capacitance variation of the inductor which is connected in parallel to the thermal sensor and results a variation of an energy stored in the inductor. Hence a variation of a converted circuit signal outputting by the output terminal is caused, wherein the variation of the converted circuit signal is correlated to the thermal variation.

Abstract: A resonance structure of bulk acoustic wave resonator comprises a bottom electrode, a dielectric layer and a top electrode, wherein the dielectric layer is formed on the bottom electrode; the top electrode is formed on the dielectric layer. A resonance area is defined by the overlapping area of the projection of the bottom electrode, the dielectric layer and the top electrode. The resonance area has a contour. The contour includes at least three curved edges and is formed by connecting the at least three curved edges. Each curved edge is concave to a geometric center of the contour.

Abstract: A semiconductor structure for improving the gate metal adhesion and the Schottky stability, comprising: a III-nitride semiconductor having a top surface on which a conductive area and a non-conductive area are defined; a source contact metal and a first drain contact metal forming ohmic contact with the III-nitride semiconductor on the conductive area, and the first drain contact metal provided at one side of the source contact metal; and a gate metal layer comprising a gate connection line and a first gate finger extending from the gate connection line, the first gate finger interposing between the source contact metal and the first drain contact metal and forming a Schottky contact with the III-nitride semiconductor on the conductive area, wherein the first gate finger has a first terminal anchor at an end thereof surrounding the source contact metal, and the first terminal anchor has an increased width.

Abstract: A package structure is disclosed. The package structure includes at least a lead, for delivering at least a signal; at least a routing layer, connected to the at least a lead, where at least a first hole is formed through the at least a routing layer; a die, disposed on the at least a routing layer, where at least a second hole is formed through the die, and the die generates or receives the at least a signal; and a molding cap, for covering the at least a routing layer and the die; where the at least a signal is delivered through the at least a first hole and the at least a second hole.

Abstract: An integrated structure of power amplifier and acoustic wave device comprises: a compound semiconductor epitaxial substrate including an epitaxial structure formed on a compound semiconductor substrate, a power amplifier upper structure formed on a top-side of a left part of the compound semiconductor epitaxial substrate, and a film bulk acoustic resonator formed on the top-side of a right part of the compound semiconductor epitaxial substrate; wherein the left part of the compound semiconductor epitaxial substrate and the power amplifier upper structure form a power amplifier; the right part of the compound semiconductor epitaxial substrate and the film bulk acoustic resonator form an acoustic wave device; the integrated structure of power amplifier and acoustic wave device on the same compound semiconductor epitaxial substrate is capable of reducing the component size, optimizing the impedance matching, and reducing the signal loss between power amplifier and acoustic wave device.

Abstract: A layout method for compound semiconductor integrated circuits, comprising following steps of: forming a first metal layer within a first circuit layout area which intersects with a second circuit layout area at an intersection area on a compound semiconductor substrate; defining an adjacent crossover area including said intersection area and a peripheral adjacent area thereof; a first dielectric area located within said adjacent crossover area and intersected with at least part of said intersection area; forming a first dielectric block within said first dielectric area or forming said first dielectric block within said first dielectric area and a second dielectric block outside said first dielectric area, the thickness of said second dielectric block is no greater than and the thickness of at least part of said second dielectric block is smaller than the thickness of said first dielectric block; forming a second metal layer within said second circuit layout area.

Abstract: An anti-plasma adhesive tape utilized for manufacturing a semiconductor package includes a substrate; and an adhesive layer formed on the substrate, wherein the adhesive layer is selected from a group composed of acrylic adhesive, light-curable resin and photoinitiator. The anti-plasma adhesive tape is attached to a backside of a lead frame of the semiconductor package before a plasma-cleaning process and removed from the lead frame after a molding process. After the anti-plasma adhesive tape is cured by irradiating an energy ray and removed from the lead frame, there is no residual adhesive left on a molding compound of the semiconductor package.

Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an “H” shaped emitter, two base electrodes, an elongated collector, and two elongated collector electrodes. The “H” shaped emitter is formed on the base mesa and has two parallel bars connected by a cross-bar. Two elongated emitter electrodes are formed respectively on the two parallel bars of the “H” shaped emitter. The “H” shaped emitter has two recesses respectively on two opposite sides of the cross-bar between the two parallel bars. The two base electrodes are formed on the base mesa respectively at the two recesses of the “H” shaped emitter, each of which has a base via hole near a center of the base mesa. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.

Abstract: An integrated structure of acoustic wave device and varactor comprises an acoustic wave device and a varactor formed on a first part and a second part of a semiconductor substrate respectively. The acoustic wave device comprises an acoustic wave device upper structure and a first part of a bottom epitaxial structure. The acoustic wave device upper structure is formed on the first part of the bottom epitaxial structure. The varactor comprises a varactor upper structure and a second part of the bottom epitaxial structure. The varactor upper structure is formed on the second part of the bottom epitaxial structure. The integrated structure of the acoustic wave device and the varactor formed on the same semiconductor substrate is capable of reducing the module size, optimizing the impedance matching, and reducing the signal loss between the varactor and the acoustic wave device.

Abstract: A semiconductor package includes a die comprising at least a via and a least a hot via; a ground lead, formed directly under a back side of the die, contacting with the back side of the die, and directly connected to the a least a hot via and the at least a via of the die; a buffer layer, formed on the die, configured to absorb a stress applied to the die and prevent the die from damage; and a molding portion, formed on the die buffer layer.

Abstract: A stacked structure comprises a semiconductor chip which includes a substrate having at least one substrate via hole penetrating through the substrate; at least one backside metal layer formed on a backside of the substrate covering an inner surface of the substrate via hole and at least part of the backside of the substrate; at least one front-side metal layer formed on the front-side of the substrate and electrically connected to the at least one backside metal layer on a top of at least one of the at least one substrate via hole; at least one electronic device formed on the front-side of the substrate and electrically connected to the at least one front-side metal layer; and at least one metal bump formed on at least one of the backside metal layer and the front-side metal layer.

Abstract: A biasing circuitry is disclosed. The biasing circuitry includes a biasing module, electrically connected to a power amplifier; and a control series, having an end electrically connected to a positive voltage, and another end electrically connected to the biasing module. The control series includes a switch unit, controlled by a control voltage to be on or off; and a voltage-drop unit, connected to the switch unit in series. The voltage-drop unit is configured to adjust a bias point of the power amplifier.

Abstract: A high-frequency package comprises a ground lead occupying a side of the high-frequency package; and a signal lead comprising at least a protrusion protruding from a central portion of the signal lead; wherein the ground lead and the signal lead perform as a transmission line, and the at least a protrusion forms capacitance of the transmission line.

Abstract: The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.