Abstract: A flash memory device and a program method thereof are provided. The flash memory device includes a memory array, a first global bit line, and a sense amplifying device. The memory array includes a first memory block having a plurality of first memory cells. In a leakage current detection operation, the sense amplifying device detects a leakage current generated by the first memory cells on the first global bit line to obtain leakage current simulation information. In a program operation, the sense amplifying device provides a reference current according to the leakage current simulation information, and compares a sensing current generated by a selected memory cell in the first memory cells on the first global bit line with the reference current to perform a program verification.

Abstract: A DRAM including a substrate, a plurality of bit line structures, and a contact is provided. The substrate has an active area. The bit line structures are arranged on the substrate, and each bit line structure at least includes a conductive structure, an insulating cover layer and a spacer. The insulating cover layer is arranged on the conductive structure. The spacer is arranged on the side wall of the conductive structure and the side wall of the insulating cover layer. The conductive structure is configured to be electrically connected to the active area. The contact is located between the bit line structures, and at least a part of the contact extends below the spacer of one of the bit line structures.

Abstract: A semiconductor memory device capable of reducing failure caused by a source side effect after a large number of W/E cycles is provided. A reading method of a NAND flash memory includes: dividing multiple word lines connected to each memory cell of a NAND string into a group 1 of word lines WL0 to WLi?1, a group 2 of word lines WLi to WLj, . . . , a group y of word lines WLj+1 to WLk?1, and a group x of word lines WLk to WLn, presetting a relationship that each readout voltage (Vread1, Vread2, . . . , Vready, and Vreadx) corresponding to each group increases toward a bit line side, and applying a readout voltage to a selected word line according to the relationship.

Abstract: A method manufacturing of a semiconductor structure including following steps is provided. A material layer is provided. A first mask layer is formed on the material layer. Core patterns are formed on the first mask layer. A spacer material layer is conformally formed on the core patterns. An etch-back process is performed on the spacer material layer. A portion of the spacer material layer located on two ends of the core pattern is removed, then spacer structures are formed. Each spacer structure includes a merged spacer and a non-merged spacer. The core patterns are removed. The first patterned mask layer is formed to cover a portion of the merged spacer and expose another portion of the merged spacer and the non-merged spacer. The first patterned mask layer and the spacer structure are used as a mask, and the first mask layer is patterned into a second patterned mask layer.

Abstract: A method for forming a semiconductor structure forming a blocking structure in the periphery region over the bottom layer. The method includes covering the middle layer over the bottom layer and the blocking structure. The method includes forming a patterned photoresist layer over the middle layer. The patterned photoresist layer is in the array region and directly over the blocking structure in the periphery region. The method includes transferring the pattern of the patterned photoresist layer to the bottom layer. The pattern of the patterned photoresist layer directly over the blocking structure is not formed in the bottom layer. The first portion of the substrate is in the array region and is an active area array. The second portion of the substrate is in the periphery region and is a guard ring. The third portion of the substrate is in the periphery region and is a periphery structure.

Abstract: A filament forming method includes: performing first stage to apply first bias including gate and drain voltages to a resistive memory unit plural times until read current reaches first saturating state, latching read current in first saturating state as saturating read current, determining whether rate of increase of saturating read current is less than first threshold value; when rate of increase of saturating read current is not less than first threshold value, performing second stage to apply second bias, by increasing gate voltage and decreasing drain voltage, to the resistive memory unit plural times until read current reaches second saturating state, latching read current in second saturating state as saturating read current and determining whether rate of increase of saturating read current is less than first threshold value; finishing the method when rate of increase of saturating read current is less than first threshold value and saturating read current reaches target current value.

Abstract: A method for forming an isolation structure includes: forming a trench at a surface of a substrate; forming a mask pattern on the substrate, wherein the mask pattern has an opening communicated with the trench; filling a first isolation material layer in the opening and the trench, wherein a surface of the first isolation material layer defines a first recess; filling a second isolation material layer into the first recess; partially removing the first and second isolation material layers, to form a second recess, performing first and second oblique ion implantation processes, to form damage regions in the first isolation material layer; performing a decoupled plasma treatment, to transform portions of the damage regions into a protection layer having etching selectivity with respect to the damage regions; and removing the damage regions.

Abstract: A package structure and its manufacturing method are provided. The package structure includes a substrate with a recess, and a first MEMS chip, a first intermediate chip, a second MEMS chip and a first capping plate sequentially formed on the substrate. The lower surface of the first MEMS chip has a first sensor or a microactuator. The upper surface of the second MEMS chip has a second sensor or a microactuator. The first intermediate chip has a through-substrate via, and includes a signal conversion unit, a logic operation unit, a control unit, or a combination thereof. The package structure includes at least one of the first sensor and the second sensor.

Abstract: The disclosure provides a semiconductor storage device and a reading method, which may achieve high-speed processing time for error detection and correction and achieve miniaturization. The flash memory of the disclosure has a NAND chip and an ECC chip. The NAND chip has: a memory array; a page buffer/sensing circuit, including latches L1 and L2; and dedicated input and output terminals, which may be used for data transmission with ECC chip. The latch L1 contains cache C0 and cache C1, and the latch L2 only contains the cache C1. The data in the cache C0 of the latch L1 and the data in the cache C1 of the latch L2 are transmitted to the ECC chip. In response to outputting data at the initial address from the ECC chip, the next page is read from the memory array, and the read data is held in the latch L1.

Abstract: Provided are a memory device and a method of manufacturing the same. The memory device includes: a stack structure; a first source/drain region and a second source/drain region located in a substrate beside the stack structure; a first self-aligned contact connected to the first source/drain region; a second self-aligned contact connected to the second source/drain region; a first liner structure located between the first self-aligned contact and a first sidewall of the stack structure; and a second liner structure located between the second self-aligned contact and a second sidewall of the stack structure. The first liner structure and the second liner structure are not connected and do not cover the stack structure.

Abstract: Provided is a memory device including a substrate, a plurality of landing pads, a protective layer, a filling layer, a plurality of cup-shaped lower electrodes, a capacitor dielectric layer, and an upper electrode. The landing pads are disposed on the substrate. The protective layer conformally covers sidewalls of the landing pads. The filling layer is laterally disposed between the landing pads, wherein the filling layer has a top surface higher than a top surface of the landing pads. The cup-shaped lower electrodes are respectively disposed on the landing pads. The capacitor dielectric layer covers a surface of the cup-shaped lower electrodes. The upper electrode covers a surface of the capacitor dielectric layer. A method of forming a memory device is also provided.

Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

Abstract: Provided is a method of manufacturing a memory device and a patterning method. The patterning method includes following steps. A control structure including stop layers and oxide layers stacked alternately, a hard mask layer, and a mask pattern are sequentially formed on a target layer. A photoresist layer is formed in the mask pattern on the hard mask layer. A portion of the hard mask layer and a portion of the control structure are removed to form first openings by using the photoresist layer and the mask pattern as a mask. The photoresist layer and the hard mask layer are removed to form a second opening having a bottom surface higher than that of the first openings. At least one etching process is performed so that the first and second openings extend into and divide the control structure and the target layer into stack structures.

Abstract: A clock-generating circuit is provided, which includes a voltage-reference circuit, a tracking-voltage-generating circuit, a voltage regulator, an oscillation generator, and a level shifter. The voltage-reference circuit and the tracking-voltage-generating circuit respectively convert the external voltage into a reference voltage and a temporary reference voltage. The voltage regulator receives the reference voltage and the temporary reference voltage, and it converts the reference voltage or the temporary reference voltage into an oscillation power-supply voltage. The oscillation generator generates a first clock signal according to the oscillation power-supply voltage. The level shifter converts a voltage amplitude of the first clock signal to generate a second clock signal that is output by the clock-generating circuit.

Abstract: The disclosure provides a semiconductor device and a reading method capable of achieving high-speed reading performance. A NAND flash memory according to the disclosure includes: a bit line selection circuit for selecting an even-numbered bit line or an odd-numbered bit line, and a page buffer/reading circuit connected to the bit line selection circuit. A reading method of a flash memory includes: precharging the selected bit line with a virtual power supply (VIRPWR) connected to the bit line selection circuit (step #1); and initializing a latch circuit (L1) through a voltage supply node V1 in parallel with the precharging of the selected bit line (step #1_2); and initializing the page buffer/reading circuit 170 through the voltage supply node V1 (step #1_3).

Abstract: A method for accessing memory and a memory device using the same method are provided. The method includes: coupling, by a first sense amplifier (SA) of a memory, to a memory cell of the memory to receive data from the memory cell; coupling a first terminal of a transistor of the memory to the first SA; coupling a first command terminal of a system on chip (SoC) to a second terminal of the transistor, and coupling a first input/output (I/O) terminal of the SoC to a third terminal of the transistor; and issuing, by the SoC, an access command to the second terminal of the transistor to access the data output by the first SA through the third terminal of the transistor.

Abstract: An evaluation circuit, a semiconductor device using the evaluation circuit, and an evaluation method using the evaluation circuit are provided to correctly measure the voltage values of individual transistors, while ensuring that there are fewer than four types of measured voltage values. The evaluation circuit includes a first switch element and a second switch element. The first switch element is disposed between a drain of the transistor and a first drain power supply. The second switch element is connected in parallel to the first switch element and disposed between the drain and a second drain power supply. A source of the transistor is electrically connected to A source power supply. A voltage applied to the second drain power supply is equal to a voltage applied to the source power supply.

Abstract: A semiconductor memory apparatus including a memory cell array, a switch circuit, and a sensing circuit is provided. The memory cell array includes multiple memory cells. The switch circuit includes at least one switch. Each of the switch receives a control signal and is turned on or off under control of the control signal. When an erase verification is performed, the sensing circuit sequentially receives an erase verification current generated by each of the memory cells through the switch circuit to verify an erase state of the each of the memory cells.

Abstract: A semiconductor structure including a substrate and a monitoring mark is provided. The substrate includes a monitoring region. The monitoring mark is located in the monitoring region. The top-view pattern of the monitoring mark includes a curved line and a recess. The curved line and the recess are opposite to each other, the curved line has a vertex, and the recess has a right-angled corner.

Abstract: A semiconductor structure includes a substrate and a buried gate structure in the substrate. The buried gate structure includes a gate dielectric layer formed on the sidewall and the bottom surface of a trench in the substrate, a barrier layer formed in the trench and on the sidewall and the bottom surface of the gate dielectric layer, a first work function layer formed in the trench and including a main portion and a protruding portion, a second work function layer formed at opposite sides of the protruding portion, and an insulating layer formed in the trench and on the protruding portion of the first work function layer and the second work function layer. The barrier layer surrounds the main portion of the first work function layer. The area of the top surface of the protruding portion is less than the area of the bottom surface of the protruding portion.