Patents Assigned to Winbond Electronics Corp
  • Publication number: 20240233819
    Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 11, 2024
    Applicant: Winbond Electronics Corp.
    Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
  • Publication number: 20240233840
    Abstract: A memory controller for controlling a flash memory is provided. The memory controller includes a control circuit and a voltage generator. The control circuit is configured to program one or more pages of the flash memory in sequence, wherein each page includes a plurality of bytes. The voltage generator is configured to adjust the output voltage according to the control signal from the control circuit. The control circuit performs a programming verification operation on each byte of a current page of the one or more pages in a page programming mode, and calculates the first number of bytes which fail the programming verification operation and performs a programming operation again. The control circuit determines the programming mode of the page after the current page as the page programming mode or the byte programming mode according to the first number.
    Type: Application
    Filed: January 6, 2023
    Publication date: July 11, 2024
    Applicant: Winbond Electronics Corp.
    Inventor: Chung-Meng HUANG
  • Publication number: 20240233809
    Abstract: A control circuit includes a control unit, a delay line unit, and a detection unit. The delay line unit delays an input clock signal based on the delay amount and generates an output clock signal. The detection unit performs a detection operation to detect the number of delayed clock cycles from the input clock signal to the output clock signal. The control unit changes the delay amount during a delay operation and controls the delay line unit so that the input clock signal is synchronized with the output clock signal. Before the delay operation, the detection unit performs the detection operation multiple times and detects a plurality of numbers of delayed clock cycles. The control unit sets the delay amount for the detection operation and sets the delay amount for the delay operation according to plurality of detected numbers of delayed clock cycles.
    Type: Application
    Filed: November 27, 2023
    Publication date: July 11, 2024
    Applicant: Winbond Electronics Corp.
    Inventor: Shinya OKUNO
  • Publication number: 20240234201
    Abstract: An isolation structure, comprising: an isolation material layer, filled in a trench of a substrate; and a protection layer, having two portions extending from a topmost surface of the substrate to a top surface of the isolation material layer across boundaries of the trench, and covering opposite edges of the isolation material layer, wherein the two portions of the protection layer are laterally spaced apart from each other, and the protection layer has an etching selectivity with respect to the isolation material layer.
    Type: Application
    Filed: March 26, 2024
    Publication date: July 11, 2024
    Applicant: Winbond Electronics Corp.
    Inventors: Che-Jui Hsu, Ying-Fu Tung, Chun-Sheng Lu, Mu-Lin Li
  • Patent number: 12032396
    Abstract: Disclosed is a voltage generating circuit including a reference voltage generating part, a leakage current monitoring part, a control part, and an internal voltage generating part. The reference voltage generating part generates a reference voltage. The leakage current monitoring part generates a monitoring leakage current corresponding to a leakage current of an internal circuit of a semiconductor device. The control part controls the reference voltage according to the monitoring leakage current. The internal voltage generating part receives the reference voltage being controlled by the control part, and supplies an internal voltage to the internal circuit according to the controlled reference voltage. A semiconductor device including the same is also disclosed.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: July 9, 2024
    Assignee: Winbond Electronics Corp.
    Inventor: Hiroki Murakami
  • Patent number: 12033681
    Abstract: A semiconductor storage device capable of achieving low power and high integration is provided. A non-volatile semiconductor memory of the disclosure includes a memory cell array. The memory cell array has a NOR array with a NOR flash memory structure and a variable resistance array with a variable resistance memory structure formed on a substrate. An entry gate is formed between the NOR array and the variable resistance array. When the NOR array is accessed, the entry gate separates the variable resistance array from the NOR array.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: July 9, 2024
    Assignee: Winbond Electronics Corp.
    Inventor: Masaru Yano
  • Publication number: 20240219465
    Abstract: A method and an apparatus for integrated circuit testing are provided. The method includes: operating a tester to perform a qualitative testing on devices in the integrated circuit by following electrical addresses of the devices, and to introduce an original verification pattern during the qualitative testing, such that a verification pattern corresponding to the original verification pattern can be converted from a raw data of a result of the qualitative testing; converting the raw data to a test graph presented by physical addresses, by using pre-determined scramble equations; and identifying portions of the verification pattern appeared in the test graph and comparing the portions of the verification pattern with corresponding portions of the original verification pattern by pattern recognition, and correcting the pre-determined scramble equations according to comparison result.
    Type: Application
    Filed: January 3, 2023
    Publication date: July 4, 2024
    Applicant: Winbond Electronics Corp.
    Inventors: Kuo-Min Liao, Tien-Yu Liao, Chien-Han Liao
  • Publication number: 20240221847
    Abstract: A non-volatile memory and an operating method thereof are provided. The non-volatile memory includes a memory array and a controller. Each main memory cell string, a first judgment memory cell string, and a second judgment memory cell string of the memory array respectively includes a plurality of main memory cells, a plurality of first judgment memory cells and a plurality of second judgment memory cells. During a programming operation, the controller determines, according to a data level of each main memory cell, a data level of the corresponding first judgment memory cell, determines, according to data levels of each first judgment memory cell and its preceding first judgment memory cell, a data level of the 10 corresponding second judgment memory cell, and accordingly determines whether to perform a pre-programming operation during an erasing operation.
    Type: Application
    Filed: November 23, 2023
    Publication date: July 4, 2024
    Applicant: Winbond Electronics Corp.
    Inventors: Yu-Cheng Chen, Chieh-Yen Wang
  • Patent number: 12027217
    Abstract: A semiconductor device and an operation method capable of operating with high reliability are provided. A voltage monitoring circuit (100) of the disclosure includes: a power-on detection part (110) configurated to detect whether a supply voltage (EXVDD) of an external power supply terminal has reached a power-on voltage level; a timer (120) configurated to measure a predetermined time when the power-on voltage level is detected; a through current generation part (130) configurated to generate a through current between the external power supply terminal and GND during a period when the timer (120) measures the predetermined time; and a power-off detection part (140) configurated to detect whether a drop of the supply voltage (EXVDD) has reached a power-off voltage level when the through current is generated.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: July 2, 2024
    Assignee: Winbond Electronics Corp.
    Inventor: Kenichi Arakawa
  • Patent number: 12027216
    Abstract: A memory, including a selected memory cell block and a first sense amplifying device, is provided. The selected memory cell block and the first sense amplifying device are both coupled to a first global bit line. The first sense amplifying device is configured to: in a leakage current detection mode, detect a leakage current of the selected memory cell block on a first global bit line to generate leakage current information; and in a data reading mode, provide a reference signal according to the leakage current information, and compare a readout signal on the first global bit line with the reference signal to generate readout data, wherein the leakage current detection mode happens before the data reading mode.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: July 2, 2024
    Assignee: Winbond Electronics Corp.
    Inventor: Wen-Chiao Ho
  • Patent number: 12029049
    Abstract: A memory device includes a substrate, an electrical channel layer, a first electrode, a resistive switching layer, a second electrode, and a conductive structure. The electrical channel layer is disposed on the substrate. The first electrode is disposed on the substrate and extends into the electrical channel layer. The resistive switching layer is disposed between the first electrode and the electrical channel layer. The second electrode is disposed on the electrical channel layer. The conductive structure connects the electrical channel layer and the second electrode.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: July 2, 2024
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Po-Yen Hsu, Bo-Lun Wu, Tse-Mian Kuo, Wei-Che Chang, Shuo-Che Chang
  • Patent number: 12027422
    Abstract: A method for forming a semiconductor structure includes: forming an active layer on a substrate; forming hard masks on the active layer, wherein a first spacing is disposed between two closely spaced hard masks in a predetermined word line region nearest to a predetermined selective gate region, wherein the first spacing is less than a second spacing between any two of the hard masks other than the two closely spaced hard masks; forming spacers on the sidewalls of the hard masks, wherein two spacers on opposite sides of the sidewalls of the closely spaced hard masks merge into a combined spacer; and transferring the patterns of the spacers to the active layer to form word lines. The step of transferring the patterns of the spacers includes transferring the pattern of the combined spacer to the active layer to form a first word line.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: July 2, 2024
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Tseng-Yao Pan, Chien-Hsiang Yu, Hung-Sheng Chen, Ching-Yung Wang, Cheng-Hong Wei
  • Publication number: 20240212988
    Abstract: A dry etching method for reducing fluorocarbon-containing gas emissions is provided. The method includes supplying a first gas to a reaction chamber to adjust a process parameter related to the reaction chamber. The method also includes supplying a second gas to the reaction chamber. The method further includes turning on a power source to ionize the second gas, thereby generating plasma. The plasma is used to remove part of a material layer on a substrate. The composition of the first gas is different from the composition of the second gas.
    Type: Application
    Filed: July 11, 2023
    Publication date: June 27, 2024
    Applicant: Winbond Electronics Corp.
    Inventors: Yuan-Hao SU, Chun-Chieh WANG, Tzu-Ming OU YANG
  • Publication number: 20240213102
    Abstract: A method for detecting a seam in a film is provided. The following process is performed on a film in a first wafer: (a) a scan is performed to obtain a gray level image; (b) a region positioning process is performed on the gray level image to define target regions and a seam region located in each target region; (c) a gray level value of each pixel in each seam region is obtained, and the number of pixels whose gray level values are lower than a gray level threshold value in each seam region is calculated; (d) a pixel quantity threshold value is generated according to the number in each seam region. Then, the process (a) to (c) is performed on a film in a second wafer, and a seam region having the number exceeding the pixel quantity threshold value is determined to be a defect region.
    Type: Application
    Filed: December 26, 2023
    Publication date: June 27, 2024
    Applicant: Winbond Electronics Corp.
    Inventors: Chih-Yu Chiang, Chi-Hung Chan
  • Patent number: 12020945
    Abstract: A semiconductor structure and its manufacturing method are provided. The method includes sequentially forming an insulating layer and a patterned mask layer on a substrate. The patterned cover curtain layer has an opening, and the opening includes a main body portion and two extension portions located at both ends of the main body portion. The method includes sequentially forming a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer on the insulating layer. The first sacrificial layer fills the extension portions and defines a recess in the main body portion. The second sacrificial layer is formed in the recess defined by the first sacrificial layer. The third sacrificial layer is formed on the first sacrificial layer located in the extension portions.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: June 25, 2024
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Kai Jen, Hsiang-Po Liu
  • Publication number: 20240204049
    Abstract: A memory device includes a stack structure disposed above a substrate. The stack structure includes a plurality of stacks and a plurality of isolation layers alternating with each other. Each stack includes: a first source and drain layer; an insulating layer disposed on the first source and drain layer; a second source and drain layer disposed on the insulating layer; and a channel layer disposed on a sidewall of the insulating layer. A lower surface of the channel layer is connected to the first source and drain layer, and an upper surface of the channel layer is connected to the second source and drain layer. The memory device further includes a gate pillar extending through the stack structure; and a charge storage structure disposed between the channel layer and the gate pillar.
    Type: Application
    Filed: December 18, 2022
    Publication date: June 20, 2024
    Applicant: Winbond Electronics Corp.
    Inventors: Ping-Lung Yu, Po-Chun Shao
  • Publication number: 20240201720
    Abstract: A voltage generating device includes a low-dropout voltage regulator and a control signal generator. The low-dropout voltage regulator provides an output voltage to a power distribution network. The low-dropout voltage regulator has a feedback circuit. The feedback circuit divides the output voltage to generate a feedback voltage according to a voltage dividing ratio, and the feedback circuit sets the voltage dividing ratio according to multiple control signals. The control signal generator is coupled to the feedback circuit and the power distribution network, and generates the control signals by comparing a sensing voltage at a reference terminal of the power distribution network with multiple threshold voltages.
    Type: Application
    Filed: December 15, 2022
    Publication date: June 20, 2024
    Applicant: Winbond Electronics Corp.
    Inventor: Chen-Yu Wu
  • Patent number: 12016173
    Abstract: A semiconductor device including a substrate, a capacitor, a stop layer, a first contact, and a second contact is provided. The substrate includes a memory array region and a peripheral circuit region. The capacitor is located in the memory array region. The capacitor includes a first electrode, a second electrode, and an insulating layer. The second electrode is located on the first electrode. The insulating layer is located between the first electrode and the second electrode. The stop layer is located on the second electrode in the memory array region and extends into the peripheral circuit region. A material of the stop layer is not a conductive material. The first contact is located in the memory array region, passes through the stop layer, and is electrically connected to the second electrode. The second contact is located in the peripheral circuit region and passes through the stop layer.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: June 18, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Te-Hsuan Peng, Kai Jen
  • Patent number: 12014799
    Abstract: The disclosure provides a semiconductor storage device that realizes high integration and improves reliability. A bit line selection circuit (100) of a flash memory includes transistors (BLSeO, BLSeE, BLSoO, BLSoE) in the column direction of bit lines (BL0-BL3), selecting a bit line pair composed of an even-numbered bit line (BL0) and an odd-numbered bit line (BL3) is selected by the transistors, in which a bit line pair (BL1, BL2) adjacent to the selected bit line pair is set as a non-selected bit line pair, and the selected bit line pair (BL0, BL3) is connected to page buffer/sensing circuit through an output node (BLS0, BLS1).
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: June 18, 2024
    Assignee: Winbond Electronics Corp.
    Inventor: Naohito Morozumi
  • Patent number: 12015059
    Abstract: A method of forming a semiconductor structure includes forming a mask layer on a substrate. The mask layer and the substrate include an opening. An isolation structure is formed in the opening. The mask layer is removed. A first conductive layer is formed on the isolation structure and the substrate. A first implantation process is performed on the first conductive layer and the isolation structure, to form a doped portion in the first conductive layer and a doped portion in the isolation structure. A second conductive layer is formed on the first conductive layer and the isolation structure. A first planarization process is performed, so that the top surfaces of the second conductive layer, the first conductive layer, and the isolation structure are aligned.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: June 18, 2024
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Che-Jui Hsu, Ying-Fu Tung