Abstract: A terminal correction circuit includes a first terminal replica model, a terminal voltage offset correction circuit, a second terminal replica model and a terminal resistance offset correction circuit. The first terminal replica model sets a resistance ratio of first and second adjustable resistors according to a voltage correction code, thereby adjusting a terminal voltage. The terminal voltage offset correction circuit compares the terminal voltage and a third power supply voltage and provides the voltage correction code according to the comparison result. The second terminal replica model sets a resistance ratio of third and fourth adjustable resistors according to the voltage correction code and reduces an equivalent resistance value between a half-voltage terminal and a ground voltage according to a resistance correction code.

Abstract: A capacitor structure includes a first capacitor device structure, a first circuit layer, and at least one second capacitor device structure. The first capacitor device structure includes a first substrate and first capacitors. The first capacitors are located in the first substrate. The first circuit layer is located on the first capacitor device structure. The at least one second capacitor device structure is located on the first circuit layer. The second capacitor device structure includes a second substrate and second capacitors. The second capacitors are located in the second substrate. The first capacitors and the second capacitors are connected in parallel by the first circuit layer.

Abstract: Provided is a method of optimizing pass voltage including: determining a sweet point of an initial pass voltage; monitoring a pulse number of ISPP; obtaining a shift of a low boundary value of the pass voltage by a shift of the pulse number of the ISPP at different cycles; monitoring a pulse number of ISPE; obtaining a shift of a high boundary value of the pass voltage by a shift of the pulse number of the ISPE at the different cycles; adding the shift of the high boundary value and the shift of the low boundary value and dividing by 2 to get a shift of the sweet point of the pass voltage; and adding the sweet point of the initial pass voltage and the shift of the sweet point of the pass voltage to obtain an optimized pass voltage value.

Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

Abstract: A forming operation of resistive memory device is provided. The operation includes: applying a pre-forming gate voltage and a pre-forming bit line voltage to a target memory cell; performing a dense switching forming operation, wherein the dense switching forming operation includes alternately performing dense set operations and dense reset operations on the target memory cell, wherein the dense set operation includes applying a dense switching gate voltage and a dense set bit line voltage; and performing a normal set operation on the target memory cell, wherein the normal set operation includes applying a normal set gate voltage and a normal set bit line voltage to the target memory cell, the normal set gate voltage is greater than the pre-forming gate voltage and the dense switching gate voltage, and the normal set bit line voltage is less than the pre-forming bit line voltage and the dense set bit line voltage.

Abstract: A dynamic sampling method and device for semiconductor manufacture are provided. The dynamic sampling method includes: generating an N-dimensional virtual image of a wafer based on a design rule and at least one of a quality control data and context data; measuring a critical pattern in the N-dimensional virtual image to generate a virtual metrology result by using a virtual metrology; determining whether the virtual metrology result is larger than a threshold; not performing a measurement on the wafer in a case that the virtual metrology result is larger than the threshold; and performing the measurement on the wafer in a case that the virtual metrology result is not larger than the threshold.

Abstract: A dynamic memory and a control method for power down scheme are provided. The control method includes: receiving a power down command at a first time point; judging whether the first time point is in an operation period of a burst refresh operation; if the first time point is not in the operation period of the burst refresh operation: calculating a time difference between the first time point and a time point of a next refresh operation according to a second time point of a previous refresh operation and a refresh operation time interval, and determining whether to activate a low power operation mode of the dynamic memory according to the time difference.

Abstract: A memory device includes a substrate, a plurality of word lines, a select gate, and a dummy word line. The word lines are located above the substrate. The select gate is located on one side of the word lines. The dummy word line is located between the word lines and the select gate. A first gap between the word lines has a first gap width. A second gap between the dummy word line and an edge word line of the word lines has a second gap width. A third gap between the dummy word line and the select gate has a third gap width. A ratio of the third gap width to the first gap width is between 0.95 and 1.05.

Abstract: A memory system includes a first memory bank. The first memory bank includes multiple first memory cells, a first switch circuit, and a first local column decoder. The first memory cells are coupled to a first bit line. The first switch circuit is configured to, according to a voltage on a first local column select line, selectively couple the first bit line to a first local data line. The first local column decoder is configured to selectively couple the first local column select line to a global column select line, and selectively couple the first local column select line to a reference ground voltage.

Abstract: A system includes an active signing server including a secure storage and processing unit and an interface. The secure storage and processing unit is configured to store a first private key, generate signatures using the first private key for authentication by devices storing a first public key forming a key pair with the first private key and sign a replacement command using the first private key, the replacement command being configured to be used to instruct the devices to replace the first public key with a second public key forming a key pair with a second private key. The interface is configured to provide the signatures to the devices and the replacement command to at least one entity, which is remote to the active signing server and the devices for storage, the at least one entity including an orchestration server and/or at least one other signing server.

Abstract: A semiconductor structure including a substrate and an isolation structure is provided. The substrate includes a device region. The isolation structure is located in the substrate. The isolation structure surrounds the device region. The isolation structure includes a first dielectric layer and a second dielectric layer. The first dielectric layer and the second dielectric layer are located in the substrate. The first dielectric layer is located between the second dielectric layer and the substrate. The second dielectric layer includes a first portion and a second portion. The second portion is located on the first portion. The distance between the second portion and the substrate in the device region is greater than the distance between the first portion and the substrate in the device region.

Abstract: A semiconductor manufacturing apparatus and a semiconductor manufacturing method thereof are provided. Wafers are grouped into a first wafer group and a second wafer group according to alignment mark position errors of the wafers and a first threshold value. The alignment mark position errors of the first wafer group are greater than the first threshold value, and the alignment mark position errors of the second wafer group are less than or equal to the first threshold value. A feedforward position correction value is calculated according to a difference between the alignment mark position errors of the first wafer group and a reference error value. A lithography process is performed on the wafers according to the feedforward position correction value.

Abstract: Disclosed is a memory chip including a plurality of first power pads and a first bus. The first bus is connected to the first power pads. One of the first power pads is coupled to the first bus via a switch device. A data width of the memory chip is determined according to a conduction state of the switch device.

Abstract: A method of forming a semiconductor structure is provided. The method includes following steps. A core pattern is formed on a target layer. Spacers are formed on sidewalls of the core pattern. The core pattern is removed to form an opening between the spacers. A portion of the target layer is removed by using the spacers as a mask to form a plurality of pairs of target patterns. After forming the pairs of target patterns, the spacers are removed, wherein a core opening is formed between each of pair of target patterns, and a gap opening is formed between adjacent pairs of the target patterns. A core capacitance value of corresponding target patterns on both sides of the core opening or a gap capacitance value of corresponding target patterns on both sides of the gap opening is measured to detect a structural uniformity of the core pattern.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, an isolation feature, and first and second word lines. The substrate has an array area and an adjacent dummy word line area. The isolation feature is disposed in the substrate in the array area and the dummy word line area to define an active region of the substrate. A first word line including first conductive structures is buried in the substrate in the dummy word line area and extends across the active region and the isolation feature. The second word line including a second conductive structure is buried in the substrate in the array area and extends across the active region and the isolation feature. A first top surface of each of the first conductive structures is below a second top surface of the second conductive structure.

Abstract: A testing circuit for testing a plurality of electrical devices is provided. The testing circuit includes a first pad and a plurality of delay circuits. The first pad is disposed on a scribe line of a substrate. The first pad is configured to receive a trigger signal to trigger the electrical devices to sequentially perform a testing operation. The electrical devices are disposed on the substrate. The delay circuits are disposed on the scribe line of the substrate. The delay circuits are electrically connected to the first pad. The delay circuits are configured to delay the trigger signal and output the delayed trigger signal to the corresponding electrical devices. The electrical devices sequentially perform the testing operation according to the delayed trigger signal to respectively output a testing result.

Abstract: A manufacturing method of a semiconductor structure including the following steps is provided. A substrate is provided. The substrate includes a front side and a back side opposite to each other. A device layer is formed on the front side of the substrate. A through-substrate via (TSV) is formed in the device layer and the substrate. The TSV extends from the front side of the substrate into the substrate. A first dielectric layer is formed between the TSV and the substrate. A patterning process is performed on the back side of the substrate to form an air gap. The air gap surrounds the TSV.

Abstract: Provided is a delay control circuit that can prevent an N-value detection sequence performed by the delay control circuit from exceeding a specific period. The delay control circuit includes: a DLL control circuit that sets a delay amount; a delay line circuit that performs a delay operation; and an N-value detection circuit that receives an input clock signal and an output clock signal and is configured to perform a pre-N-value detection operation. The pre-N-value detection operation includes detecting the number of delayed clock cycles from the input clock signal to the output clock signal as the number of pre-delayed clock cycles before a delay operation is performed. In response to that the number of pre-delayed clock cycles is not greater than a specific value, the DLL control circuit changes the delay amount so that the delay line circuit performs the delay operation in a fast mode.

Abstract: A polishing pad and a chemical mechanical polishing apparatus are provided. The polishing pad includes: a central portion, designed with a central recess; and a peripheral portion surrounding the central portion, and designed with at least one peripheral recess. The at least one peripheral recess is disposed along an annulus contour. A lower part of the peripheral recess is greater than an upper part of the peripheral recess in terms of diameter area, and is different from the upper part in shape.

Abstract: A memory device including a substrate, a plurality of stack structures, and a protective layer is provided. The plurality of stack structures are arranged along a first direction on an array area of the substrate, and each of the stack structures extends along a second direction different from the first direction. In a cross-sectional view of the memory device, each of the stack structures includes, in sequence from the substrate, a charge storage structure, a control gate, and a cap layer. The cap layer has a multilayer structure. The protective layer covers sidewalls of the stack structures. A width in the first direction of the charge storage structure, a width of the control gate, and a width of the cap layer are substantially equal to each other.