Abstract: A method for reducing wafer edge defects is provided. The method includes providing a wafer with a central region and an edge region, forming a hard mask layer on the wafer, forming a spacer pattern on the hard mask layer, forming a photoresist layer covering the spacer pattern, performing a wafer edge treatment process on the photoresist layer to form an annular photoresist pattern, using the annular photoresist pattern as an etching mask, and sequentially transferring the exposed spacer pattern to the hard mask layer and the wafer to form a plurality of trenches in the wafer.

Abstract: A RRAM and its manufacturing method are provided. The RRAM includes a first dielectric layer formed on a substrate, and two memory cells. The two memory cells include two bottom electrode structures separated from each other. Each bottom electrode structure fills one of two trenches in the first dielectric layer. The two memory cells also include a resistance switching layer and a top electrode structure. The resistance switching layer is conformally formed on the surface of an opening in the first dielectric layer, and the opening is between the two trenches. The top electrode structure is on the resistance switching layer and fills the opening. A top surface of the first dielectric layer, top surfaces of the bottom electrode structures, a top surface of the resistance switching layer, and a top surface of the top electrode structure are coplanar.

Abstract: A phase change memory (PCM) in which the phase change storage element is crystallized by a gradually increasing/decreasing operating current. The PCM comprises a switching circuit, the phase change storage element, a bit select switch, a pulse generating module, and a counting module. The switching circuit comprises a plurality of switches, selectively providing branch paths to an output terminal of a current source. The bit select switch controls the conduction between the phase change storage element and the output terminal of the current source. The pulse generating module outputs a pulse signal oscillating between high and low voltage levels. When enabled, the counting module counts the oscillations of the pulse signal, and outputs the count result by a set of digital data. The set of digital data are coupled to the switching circuit to control the switches therein.

Abstract: An embodiment of a method for driving a phase change memory, comprising counting an access number of a phase change memory, wherein the access number is the number of times that the phase change memory has been accessed; refreshing the phase change memory when the number of times is large than a predetermined number.

Abstract: ESD protection devices and methods of forming them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process and breakdown-enhanced layers, ESD protection devices with a lower trigger voltage are provided. The NMOS structure for ESD protection according to the present invention has islands, a control gate and breakdown-enhanced layers. These islands as well as the breakdown-enhanced layers overlapping the drain region of the NMOS reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.

Abstract: The present invention provides a kind of contactless and intelligence-wise code identification chip system. The contactless and intelligence-wise code identification chips have an identification code respectively. The chips can generate a random number to select one of time slots for allocating said identification code. The contactless and intelligence-wise code reader can read the identification code from time slots by the polling method.

Abstract: An optimal algorithmic structure is provided for use in a RAKE receiver to compute multipath interferences (MPIs) required for canceling intra-codeword chip interference (ICI). The algorithmic structure jointly computes the ICI of a plurality of possible codewords. This algorithmic structure is similar to the optimal architecture required for CCK correlation computations. The similarity between these two structures allows for the use of the same hardware at different times to compute MPIs and to compute the CCK correlation of a plurality of possible codewords.

Abstract: The present invention relates to an image-decoding method and device thereof. The image-decoding device includes a memory, a modifying means, a decoding unit, an image reconstruction unit and a display controller. The image-decoding device includes the steps of capturing the B-frame data and the reference frame data form plural digital image data in the memory, decoding a first field data for obtaining a decoded first field data, and decoding a second field data by means of referring the decoded first field data and the reference frame data for obtaining a decoded second field data overwriting the decoded first field data.

Abstract: An improved split gate flash memory cell is disclosed whose floating gate is formed to have a reentrant angle such that its width increases with increased distance from the substrate so as to minimize the possibility of defects in the poly oxide layer overlaying the floating gate.

Abstract: A process for making split-gate semiconductor flash memory contains an outwardly-diverging control gate stacked on but separated from a pair of opposing floating gates via an interpoly dielectric layer.

Abstract: An interconnect structure for use in semiconductor devices, comprising: (a) a thin and elongated aluminum wire connected to a first metal structure; and (b) a plurality of regularly spaced dummy tungsten plugs which are connected to the aluminum wire at one end and are buried in an underlying dielectric layer so that it is insulated at the other end. The dummy tungsten plugs absorb the mobile aluminum atoms generated through stress-induced migration when the interconnect structure is subject to a rapid temperature change, thus preventing the via bulging problem which could seriously damage the second metal structure above the first metal structure.

Abstract: A bond pad structure for use in wire bonding application during the packaging operation of semiconductor devices which contains a bond frame structure for holding the bond pad in place to prevent bond pad peel-off problem. The bond pad structure is a laminated structure containing a top dielectric layer, a metal bond pad layer, a middle dielectric layer, and an underlying layer formed above a wafer surface. The bond frame structure, which is formed in a spaced apart relationship from the metal bond pad layer contains a plurality of island elements formed on top of the middle dielectric layer and an interconnected frame element formed on top of the top dielectric layer. The frame element contains a portion which overlaps with a portion of the metal bond pad layer, so as to exert a downward force to prevent the metal bond pad layer from peeling off.

Abstract: A fuzzy processor which can be programmed and expanded is disclosed. The fuzzy processor has a membership function I/O circuit for inputting and outputting a plurality of membership functions respectively corresponding to each one of a plurality of features of each one of a plurality of standard patterns. A feature decoder receives a to-be-recognized pattern having a plurality of input features for generating a plurality of feature values. A membership function generator stores the plurality of membership functions and receives the plurality of feature values to generate a plurality of current-type membership degrees for the plurality of input features corresponding to the plurality of standard patterns respectively. A plurality of accumulators receive the plurality of current-type membership degrees respectively for generating a plurality of synthesis membership degrees.

Abstract: A process for making self-aligned split-gate non-volatile memory cell is disclosed. It includes the step of using a nitride photomask in conjunction with a photoresist to etch the nitride layer and cause it to become a stepped nitride layer having a high thickness region and a low thickness. Then a poly-1 photomask is used in conjunction with a photoresist to etch through a first portion of the low thickness region to expose an underlying poly-1 layer intended to be floating gate, wherein at the same time, a portion of the high thickness region adjacent to the first portion of the low thickness region is also etched to a reduced thickness. After poly-1 oxidation, a cell drain photomask is used in conjunction with a photoresist to etch through a second portion of the low thickness region using a nitride etch and an underlying poly-1 layer using a poly etch.

Abstract: A bond pad structure for use in wire bonding applications during the packaging of semiconductor devices with reduced bond pad lift-off problem. It includes: (a) a laminated structure containing a metal bond pad layer, a dielectric layer, and an underlying layer formed on a wafer surface; and (b) a single anchoring structure formed in said dielectric layer connecting said metal bond pad layer and said underlying layer. The single anchoring structure contains a plurality of line segments that are interconnected so as to form said single anchoring structure. Unlike prior art anchoring structures, which always contain a plurality of anchors buried inside the dielectric, the bond pad structure contains only a single anchoring structure, which can have the geometry of an open or closed ring with whiskers, a coil, an open or closed square-waved ring, a tree structure, a grid-line structure, a meandering structure, a serpentine structure, a spiral structure, or a labyrinth.

Abstract: An embedded memory control circuit is provided for use with a memory module consisting of a number of partly-defective memory chips to allow these partly-defective memory chips to be combined for use as a single memory unit with the same address space of each nondefective memory chip. The embedded memory control circuit includes a bank-select unit, a bank-suppress unit, and a data output buffer. The bank-select unit is capable of detecting whether each of the banks in the memory module is defective or nondefective to thereby generate a plurality of corresponding bank-status signals each indicative of whether the corresponding bank is defective or nondefective. The bank-suppress unit is capable of, in response to the bank-status signals and the bank-select signal, generating a plurality of defective-bank suppressing signals which can suppress each defective bank in the memory module, if any.

Abstract: A spectroscopic method is disclosed to provide a non-intrusive and in-situ monitoring of plasma etching conditions during the fabrication of semiconductor devices using RF power. It includes the steps of: (a) selecting a single plasma gas as a probe, in a cleaned plasma etch chamber; (b) measuring the spectral intensities of the plasma gas; and (c) plotting the measured spectral intensities either directly or indirectly against the RF time. A single plasma gas is selected which exhibits opposite relationships with RF time at two respective wavelengths.

Abstract: A method for monitoring the presence of particles in a plasma etch chamber. It includes the steps of: (a) selecting at least one laser light source whose wavelength is at such an energy which will cause the particles to be monitored inside the plasma etch chamber to emit Raman, Stoke, and anti-Stoke spectra lines when the laser light is scattered by the particle; (b) emitting the laser light into an internal space of the plasma etch chamber; and (c) using a set of fiber optics to intercept light that may be scattered by the particle, if the particle is present in the plasma etch chamber; and (d) measuring amplitude and spectra of the scattered light. Because the intensity of the scattered light is proportional to the dielectric constant to the fourth power, the method is most advantageous for detect the presence of metal-containing particles, which have a very high dielectric constant. The spectral analysis also provides information relating to the chemical composition of the particles.

Abstract: A wafer planarization process which utilizes combined high density plasma chemical vapor deposition (HDP-CVD) process and chemical mechanical polishing (CMP) process is disclosed. This process includes the steps of (a) forming a first HDP-CVD layer on the surface of a semiconductor wafer using a first HDP-CVD composition having a higher etching/depositing component ratio and thus a lower CMP removal rate; (b) forming a second HDP-CVD layer on the first HDP-CVD layer using the same HDP-CVD process but with a second HDP-CVD composition having a highest etching/depositing component ratio and thus the lowest CMP removal rate; (c) forming a third HDP-CVD layer on the second HDP-CVD layer using the same HDP-CVD process but with a third HDP-CVD composition having a low etching/depositing component ratio and thus a high CMP removal rate; and (d) using a chemical mechanical process to remove at least a part of the third HDP-CVD layer using the second HDP-CVD layer as a stopper.

Abstract: A method for fabricating a load device on an SRAM is provided which substantially increases the effective length of its load device without increasing the cell size.