Abstract: An encoding method for a memory storage apparatus adopting an ECC algorithm is provided. The memory storage apparatus comprises an ECC encoder. The encoding method includes: receiving a write command comprising a write address and a write data; reading an existing codeword; attaching a flip bit to the write data; encoding the write data and the flip bit to generate parity bits based on the ECC algorithm by the ECC encoder and attaching the write data and the flip bit to the plurality of parity bits to generate a new codeword; flipping the new codeword based on a number of bits among selected bits required to be changed from the existing codeword to the new codeword; and writing one of the new codeword and the flipped new codeword to the write address. In addition, a memory storage apparatus using the encoding method is provided.
Abstract: A latency control circuit and method are provided. The latency control circuit includes a DLL circuit, a latency counter circuit, a synchronization circuit, and a delay line circuit. The DLL circuit enters an inactive state after locking the delay time and provides an active signal at a disable state, delay locking information and loop delay information during the inactive state. The synchronization circuit stops providing a first clock signal according to the active signal at the disable state and then synchronously outputs an operation enabling signal and a second clock signal in response to an enablement of the operation signal. The delay line circuit receives the delay locking information, the operation enabling signal, and the second clock signal and outputs an operation delay signal and an output clock signal after the delay time.
May 8, 2020
Date of Patent:
May 11, 2021
Winbond Electronics Corp.
Young-Tae Kim, Chan-Seok Park, Youngjoo Choi, Myung-Chan Choi
Abstract: Provided is a method of fabricating a semiconductor device, including the following steps. A first seal ring and a second seal ring that are separated from each other are formed on a substrate. A protective layer covering the first seal ring and the second seal ring is formed on the substrate. The protective layer between the first seal ring and the second seal ring includes a concave surface. The protective layer at the concave surface and a portion of the protective layer on the first seal ring are removed to form a spacer on a sidewall of the first seal ring, and form an opening in the protective layer. The width of the opening is greater than the width of the first seal ring, and the opening exposes a top surface of the first seal ring and the spacer.
Abstract: A memory device including a self-test circuit, a memory cell array, a power voltage generator, and a redundant row address replacement circuit is provided. The self-test circuit is configured to generate a self-test data signal and a power voltage control signal. The memory cell array receives the self-test data signal and outputs a self-test failure signal. The power voltage generator generates a word line power voltage according to a power voltage control signal. The redundant row address replacement circuit receives the word line power voltage and the self-test failure signal to provide a redundant word line address to the memory cell array. The power voltage generator is configured to provide the word line power voltage in a built-in self-test (BIST) mode to be lower than the word line power voltage in a normal mode.
Abstract: A patterning method includes sequentially forming a target layer, a first layer, a second layer, a third layer, and a first mask pattern. A first spacer is formed on a sidewall of the first mask layer. The first mask pattern is removed to form a plurality of peripheral openings surrounding a central opening in the first spacer. A rounding process is performed to round the peripheral openings and form a second mask pattern. A portion of the second layer is removed by using the second mask pattern as a mask, so as to form a third mask pattern. A second spacer is formed in the third mask pattern. The third mask pattern is removed. Portions of the first layer and the target layer are removed by using the second spacer as a mask.
Abstract: The memory structure includes a substrate, an isolation structure disposed in the substrate; a word line trench; and a word line disposed in the word line trench. The word line has an upper gate and a lower gate. The upper gate includes an upper gate dielectric layer; an upper gate liner disposed on the upper gate dielectric layer; and an upper gate electrode disposed on the upper gate liner. The lower gate includes a lower gate dielectric layer; a lower gate liner disposed on the lower gate dielectric layer; and a lower gate electrode disposed on the lower gate liner. The vertical distance between the top surface of the upper gate dielectric layer and the bottom surface of the word line trench is not greater than that between the top surface of the upper gate electrode and the bottom surface of the word line trench.
Abstract: A dynamic random access memory (DRAM) including a substrate, transistors, bit line sets, conductive structures, and word line sets is provided. The transistors are arranged on the substrate in an array. Each transistor includes a first conductive layer, a second conductive layer, and a third conductive layer. The bit line sets are disposed in parallel along a Y direction and pass through the transistors. Each bit line set includes a first bit line and a second bit line electrically connected to the first conductive layer of each transistor respectively. The conductive structures are located in the transistors. The conductive structures are electrically connected to the second conductive layer of the transistors and the substrate. The word line sets are disposed in parallel along an X direction. Each word line set includes a first word line and a second word line located on sidewalls of each transistor respectively.
Abstract: The disclosure is directed to a memory storage device and an automatic error repair method thereof. In an aspect, the memory storage device includes a connection interface configured to receive a write command and a word line address associated with the write command, a memory array including a memory bank which contains an error correction code (ECC) detector, a plurality of memory cells controlled by a word line address, and a plurality of redundant memory cells controlled by a redundant word line address, a fuse blowing controller configured to receive the word line address to blow an electrical fuse of the word line address to enable the plurality of redundant memory cells, and a memory control circuit configured to transfer data from the plurality of memory cells through a bit line into the plurality of redundant memory cells in response to the electrical fuse having been blown.
Abstract: The present invention provides a short-circuit probe card, including: a substrate having an upper surface and a lower surface; a plurality of first contacts formed on the upper surface; and a plurality of second contacts formed on the lower surface and connected to the plurality of first contacts. The first contacts and second contacts are all grounded.
Abstract: A method of monitoring a semiconductor process includes the following steps. A process parameter is set to a first condition. A first process is performed to form a first film layer on a first wafer. The first film layer does not cover a wafer edge region of the first wafer. The first wafer having the first film layer is photographed by an image capturing device to obtain a first wafer image. Image recognition is performed to the first wafer image to obtain first data. Whether a position of the first film layer is offset is determined according to the first data.
Abstract: A reference voltage generation circuit of the invention includes: PMOS transistors P1 and P2 configured to provide current sources with same current to a first current path and a second current path; a bipolar transistor Q1 connected to the PMOS transistors P1 on the first current path; a bipolar transistor Q2 connected to the PMOS transistors P2 on the second current path; a differential amplifier AMP controlling the gates of the PMOS transistors P1 and P2, such that a voltage of a node VN and a voltage of a node VP are equal; an output node BGR outputting a reference voltage Vref; and a reference voltage guarantee portion 130 outputting a detecting signal BGRDET when a differences between the voltage of the node VN and the voltage of the node VP is maintained below a determined value.
Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a plurality of gate structures, a plurality of dielectric structures, and spacers. The plurality of gate structures is disposed on the substrate. The plurality of dielectric structures is respectively disposed between the gate structures and the substrate, wherein a top width of the dielectric structure is less than the bottom width of the dielectric structure. The spacers are disposed on the sidewalls of the gate structures and cover the sidewalls of the dielectric structures.
October 24, 2018
Date of Patent:
April 20, 2021
Winbond Electronics Corp.
Keng-Ping Lin, Tzu-Ming Ou Yang, Shu-Ming Li, Tetsuharu Kurokawa
Abstract: A delay lock loop and a phase locking method thereof are provided. The delay lock loop includes a first divider, a delay line, a frequency multiplier, a second divider, a phase detection and controlling circuit and a setting signal generator. The first divider generates a divided reference clock signal. The second divider generates a first feedback clock signal and a second feedback clock signal which are complementary by dividing an output clock signal, and generates a selected feedback clock signal by selecting the first or second feedback clock signal according to a setting signal. The phase detection and controlling circuit compares phases of the selected feedback clock signal and the divided reference clock signal to generate a delay control signal. The setting signal generator samples the divided reference clock signal by the first feedback clock signal to generate the setting signal.
Abstract: A protection method is provided to make it difficult to reverse engineer operational information. The present invention provides a protection method for preventing reverse engineering, including: generating an expected value during normal operation; monitoring voltage waveforms at monitoring points of the semiconductor integrated circuit; comparing a measured value generated in the monitored voltage waveforms with the expected value; determining whether reverse engineering is taking place or not based on comparison results; and when reverse engineering is taking place, controlling the semiconductor integrated circuit to run in a protection mode, which different from its normal operation.
Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric layer and a through hole passing through the first dielectric layer over a substrate; forming a plurality of dummy contacts in the through hole; forming a plurality of first dummy wires on the plurality of dummy contacts; filling a second dielectric layer between the plurality of first dummy wires, wherein the second dielectric layer has a first air gap; removing the dummy contacts and the first dummy wires to expose the through hole, thereby forming a first wiring trench over the through hole; and forming a contact and a first wire in the through hole and the first wiring trench.
Abstract: In an aspect of the disclosure, a reference voltage holding circuit is provided. The reference voltage holding circuit is for maintaining a sense amplifier reference voltage provided by a sense amplifier reference circuit, and the reference voltage holding circuit includes: a reference voltage generating circuit configured to provide a bias reference voltage; a current generating circuit electrically coupled to the reference voltage generating circuit and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and a voltage pull-up circuit electrically coupled to the current mirror circuit and configured to provide for the standby bias current and to maintain the standby bias voltage which drives the sense amplifier reference voltage when reference voltage holding circuit operates under a standby operation and approximates the sense amplifier reference voltage as long as the sense amplifier reference voltage remains enabled.
Abstract: A memory circuit and a semiconductor device are provided. The memory circuit has a function of recovering data when power is suddenly shutdown. The memory device includes a bi-stable circuit capable of holding complementary data respectively at nodes N1 and N2; a first non-volatile memory circuit, connected to the node; and a second non-volatile memory circuit connected to the node. The first non-volatile memory circuit stores boot data, and the second non-volatile memory circuit inverts a logic level of the data held at the second node when the second non-volatile memory circuit stores data at the second node.
Abstract: A resistive memory apparatus and an adjusting method for write-in voltage thereof are provided. The adjusting method for write-in voltage includes: selecting an under test memory cell array in a resistive memory; performing N reset operations on a plurality of memory cells of the under test memory cell array according to a reset voltage, and performing N set operations on the memory cells of the under test memory cell array according to a set voltage, wherein n is an integer greater than 1; calculating a reset time variation rate of the reset operations and a set time variation rate of the set operations; and adjusting a voltage value of one of the set voltage and the reset voltage according to the reset time variation rate and the set time variation rate.
Abstract: Provided is a semiconductor package including first to third semiconductor dies, first to third RDL layers, conductive vias and an encapsulant, and a manufacturing method thereof. The first RDL layer is on an active surface of the first semiconductor die. The second semiconductor die is on the first RDL layer and electrically connected thereto through first TSVs. The conductive vias are on the first RDL layer and around the second semiconductor die. The encapsulant encapsulates the second semiconductor die and the conductive vias. The second RDL layer is on the encapsulant. The third semiconductor die is on the second RDL layer and electrically connected thereto through second TSVs. The third RDL layer is on the third semiconductor die. The area of the second semiconductor die is smaller than that of the first semiconductor die. The area of the third semiconductor die is larger than that of the second semiconductor die.
Abstract: A memory chip including a memory bank, an address decoder circuit and a control circuit is provided. The memory bank includes a first sub-bank coupled to a first word line and a first access line and a second sub-bank coupled to a second word line and the first access line. The first sub-bank outputs data to the first access line via a first path. The second sub-bank outputs data to the first access line via a second path. The address decoder circuit decodes an external address to generate a row address and a column address. The control circuit controls the first path and the second path according to the row address and the column address. In response to the row address indicating the first word line and the column address indicating the first access line, the control circuit turns on the first path and turns off the second path.