Abstract: A linear regulator device and a configuration method thereof are provided. The linear regulator device includes a digital-to-analog converter (DAC), an operational amplifier (OPAMP), a switch, and a resistor. The DAC provides a controlled current according to a control signal. An inverting input node of the OPAMP is coupled to the DAC. An output node of the OPAMP is an output node of the linear regulator device. Input nodes of the switch are received multiple reference voltages respectively. The control signal is received by a control node of the switch. The output node of the switch is coupled to a non-inverting input node of the OPAMP. The resistor is coupled between the output node and the inverting input terminal of the OPAMP. A current inversion point of the linear regulator device is determined by one of the multiple reference voltages corresponding to the control signal and the controlled current.

Abstract: Provided is a semiconductor structure including multiple pairs of target patterns, a first conductive line, and a second conductive line. Each of the pairs of target patterns includes a top pattern and a bottom pattern. The first conductive line is disposed on a first side of the pairs of target patterns. The first conductive line is electrically connected to a top pattern of a (aN+1)th pair of target patterns in the pairs of target patterns, a is a fixed integer greater than or equal to 2, and N is an integer greater than or equal to 0. The second conductive line is disposed on a second side of the pairs of target patterns opposite to the first side. The second conductive line is electrically connected to a bottom pattern of the (aN+1)th pair of target patterns in the pairs of target patterns.

Abstract: A semiconductor memory device having a capability of adjusting slew rate of data voltage signals generated by output buffers having different PVT characteristics based on ZQ calibration signal is provided. The semiconductor memory device includes a memory, a calibration counter, a slew rate (SR) control circuit and an output buffer. The calibration counter receives a ZQ calibration signal and generates a SR calibration signal based on the ZQ calibration signal. The memory is coupled to the SR control circuit. The SR control circuit is coupled to the output buffer and the calibration counter, and configured to receive the SR calibration signal from the calibration counter. The output buffer is configured to generate a data voltage signal according to data obtained from the memory and perform a slew rate control on the data voltage signal based on the SR calibration signal.

Abstract: A flash memory apparatus and an ERASE method thereof are provided. The ERASE method includes: applying an ERASE voltage to a target memory block and determining whether an ERASE verification passes during an ERASE operation period; determining whether the target memory block meets a degradation condition when the ERASE verification fails; determining whether the target memory block passes a soft-program verification when the degradation condition is met, and returning to the step of applying the ERASE voltage after the target memory block passes the soft-program verification; returning to the step of applying the ERASE voltage when the target memory block does not meet the degradation condition; and determining whether the target memory block passes the soft-program verification when the ERASE verification passes, and applying a soft-program voltage to the target memory block after the soft-program verification fails.

Abstract: Disclosed are a method and an apparatus for memory testing. The method comprises following steps: using a test program group including N test programs to test M dies respectively to generate independent N test data, wherein N and M are positive integers greater than 1; and executing a neural network operation on the N test data to estimate a yield of M dies passing the test program group.

Abstract: A pseudo-static random-access memory is provided. A count-and-command decoder starts counting a clock signal when an internal enable signal changes from a disable state to an enable state, and outputs a column address strobe signal at a first level when the count reaches a first clock amount. During a period starting from when the column address strobe signal changes from a second level to the first level to when the internal enable signal changes from the enable state to the disable state, a burst-length counter counts the clock signal to provide a burst length accordingly. A delay control circuit outputs a first confirmation signal at the first level to a row-and-column control circuit, such that a length of a column select signal is equal to the burst length.

Abstract: A semiconductor memory device and a test method thereof are provided. The semiconductor memory device includes a plurality of word lines, a row decoder, a first voltage pump circuit, a first programmable current comparator and a control circuit. The row decoder decodes a row address data and accordingly selects a test word line to be electrically connected to a first test path. The first voltage pump circuit is configured on the first test path and applies a test voltage to the test word line. The first programmable current comparator compares a test current flowing through the first test path with a programmable reference current to provide a test result signal. The control circuit uses the word lines as the test word line sequentially, compares the corresponding test current with the programmable reference current and determines whether the test word line is defective according to the test result signal.

Abstract: A semiconductor storage apparatus having a function of emulating an erasing operation of a flash memory is provided. A resistive random access memory of the disclosure includes: a memory cell array; a controller that reads or writes the memory cell array according to an input of command; an erasing command allowance register that sets whether or not to receive an erasing command; and a busy time adjustment register that adjusts a busy time. In a case of setting to allow a reception of the erasing command, the controller responds to an input of the erasing command to emulate the erasing operation, and specifies busy information including the busy time adjusted by the busy time adjustment register.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a BEOL layer, a plurality of first metal structures and a plurality of second metal structures. The substrate has a first side and a second side opposite to the first side. The BEOL layer is disposed on the first side of the substrate. The first metal structures penetrate the substrate. The second metal structures are disposed in the substrate, extending from the second side towards the first side of the substrate, corresponding to the first metal structures.

Abstract: A manufacturing method of a memory structure including the following steps is provided. A substrate is provided. The substrate includes a memory array region. A bit line structure is formed in the memory array region. The bit line structure is located on the substrate. A contact structure is formed in the memory array region. The contact structure is located on the substrate on one side of the bit line structure. A stop layer is formed in the memory array region. The stop layer is located above the bit line structure. A capacitor structure is formed in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. The bottom surface of the capacitor structure is lower than the bottom surface of the stop layer.

Abstract: A semiconductor structure including a substrate, a first electrode, a first dielectric layer, and a second electrode is provided. The first electrode is located on the substrate. The first electrode is pillar-shaped. The first dielectric layer is located on the first electrode. The second electrode is located on the first dielectric layer. The second electrode includes a first silicon germanium (SiGe) layer and a second SiGe layer. The first SiGe layer is located on the first dielectric layer. The second SiGe layer is located on the first SiGe layer. A content of germanium in the second SiGe layer is greater than a content of germanium in the first SiGe layer.

Abstract: An operation method for a memory device is provided. A memory block of the memory device includes an array of memory cells including cell strings and cell pages. Serially numbered and arranged bit lines are connected to the cell strings, respectively. Serially numbered and arranged word lines are connected to the cell pages, respectively. The operation method includes: performing a batch writing to each of the cell pages, such that the memory cells in each cell page are respectively grouped as an earlier written memory cell or a later written memory cell, depending on the connected bit line is either even-numbered or odd-numbered. Each cell page has a respective write sequence. In terms of write sequence, each cell page is identical with one of 2 nearest cell pages, and opposite to the other of the 2 nearest cell pages.

Abstract: An etching method of etching apparatus is disclosed. The etching apparatus performs an etching process on a material to be processed which includes a material layer and a mask layer formed on the material layer. The etching method includes the following steps. The mask layer is etched. A light intensity at a specific wavelength for light generated is detected when the etching process is performed on the mask layer to be processed and an end point detection signal is generated. An etching completion time of the mask layer to be etched is determined according to the end point detection signal. A thickness of the mask layer to be etched is calculated according to the etching completion time. An etching time of the material layer is adjusted according to the thickness of the mask layer to be etched. The material layer is etched after adjusting the etching time.

Abstract: A NAND flash memory and manufacturing method thereof are provided. The NAND flash memory is capable of preventing a short circuit between gates extending along a vertical direction. The NAND flash memory includes a substrate; a plurality of channel stacks formed on the substrate and extending along an X direction; an interlayer dielectric formed between the channel stacks; a plurality of trenches formed apart from each other in the interlayer dielectric and arranged along a Y direction; an insulator stack including a charge storage layer formed to cover sidewalls of each of the trenches; and a plurality of conductive vertical gates elongating along the vertical direction in a space formed by the insulator stack in each of the trenches and extending along the Y direction.

Abstract: The method for forming the semiconductor structure includes the following steps. A substrate that is divided into a cell region and a peripheral region is provided. A bottom dielectric layer is formed on the substrate. A first stacked structure and a second stacked structure are formed on the bottom dielectric layer. The first stacked structure is disposed in the cell region and the second stacked structure is disposed in the peripheral region. The first stacked structure is patterned to form first conductive stacks. A first cleaning process is performed. A first repair dielectric layer is formed on the first conductive stacks, the second stacked structure, and the bottom dielectric layer. The second stacked structure is patterned to form second conductive stacks. A second cleaning process is performed. A second repair dielectric layer is formed on the first conductive stacks, the second conductive stacks, and the bottom dielectric layer.

Abstract: A Row Hammer Refresh Address (RHA) calculation method, calculation circuit, and semiconductor memory device that are capable of performing RHA calculation at high speed on a small circuit scale are provided. The control unit of the RHA calculation circuit preferentially calculates the address obtained using a lighter operation (merely by inverting the least significant bit) as the adjacent RHA between the adjacent RHAs on both sides based on the refreshed seed address when the seed address is refreshed. Alternatively, it preferentially calculates the address obtained using a lighter operation (merely by inverting the least significant bit) as the further adjacent RHA between the further adjacent RHAs on both sides based on the refreshed seed address when the seed address is refreshed.

Abstract: A flash memory device includes a memory array, a first global bit line, and a sense amplifying device. The memory array includes a first memory block having a plurality of first memory cells. In a leakage current detection operation, the sense amplifying device detects a leakage current generated by the first memory cells on the first global bit line to obtain leakage current simulation information. In a program operation, the sense amplifying device provides a reference current according to the leakage current simulation information, and compares a sensing current generated by a selected memory cell in the first memory cells on the first global bit line with the reference current to perform a program verification.

Abstract: A refresh control circuit includes a clock signal generator, a plurality of pulse number adjusters and a plurality of address counters. The clock signal generator generates a clock signal. The pulse number adjusters receive the clock signal, and during a time period, respectively generate a plurality of adjusted clock signals by adjusting pulse number of the clock signal according to a plurality of data retention information. The address counters respectively generate a plurality of refresh address information according to the adjusted clock signals. The refresh address information respectively correspond to a plurality of memory banks of a memory device.

Abstract: A method of fabricating a semiconductor device includes the following steps. A plurality of doped regions are formed in a substrate. A first dielectric layer is formed on the substrate. A plurality of first contacts and second contacts are formed in the first dielectric layer to be connected to the plurality of doped regions. A memory element is formed on the first dielectric layer. The memory element is electrically connected to the second contact. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer surrounds the memory element. A conductive line is formed in the second dielectric layer. A top surface of the conductive line is at a same level as a top surface of the memory element, and the conductive line is electrically connected to the plurality of first contacts.

Abstract: Provided is a semiconductor device including: a substrate, a plurality of isolation structures, a plurality of channel layers, and a gate structure. The substrate includes a plurality of fins thereon. The plurality of isolation structures are respectively disposed between the plurality of fins. A top surface of the plurality of isolation structures is higher than a top surface of the plurality of fins to form a plurality of openings. The plurality of channel layers are respectively disposed in the plurality of openings. Each channel layer is in contact with a corresponding fin and extends to cover a lower sidewall of a corresponding isolation structure, thereby forming a U-shaped structure. The gate structure is filled in the plurality of openings and extends to cover the top surface of the plurality of isolation structures.