Abstract: A forming operation of resistive memory device is provided. The operation includes: applying a pre-forming gate voltage and a pre-forming bit line voltage to a target memory cell; performing a dense switching forming operation, wherein the dense switching forming operation includes alternately performing dense set operations and dense reset operations on the target memory cell, wherein the dense set operation includes applying a dense switching gate voltage and a dense set bit line voltage; and performing a normal set operation on the target memory cell, wherein the normal set operation includes applying a normal set gate voltage and a normal set bit line voltage to the target memory cell, the normal set gate voltage is greater than the pre-forming gate voltage and the dense switching gate voltage, and the normal set bit line voltage is less than the pre-forming bit line voltage and the dense set bit line voltage.

Abstract: A manufacturing method for a semiconductor device is provided. The method includes: forming a recess at a top surface of a substrate; forming a channel layer and a barrier layer in order, to conformally cover surfaces of the recess; filling up the recess with a conductive material; removing a top portion of the conductive material, such that a lower portion of the conductive material remained in the recess forms a gate electrode; and forming an insulating structure on the gate electrode. A hetero junction formed at an interface of the channel layer and the barrier layer is external to the substrate, and a two dimensional electron gas or a two dimensional hole gas is induced along the hetero junction external to the substrate.

Abstract: A composite material including a nanocellulose core and a metal shell is provided. The metal shell covers a surface of the nanocellulose core. The composite material is nanosized and has high mechanical strength. Additionally, a method of manufacturing the composite material is also provided.

Abstract: An AND type flash memory is provided. The AND type flash memory includes a plurality of memory cells connected in parallel between a source line and a bit line. The memory cell includes a charge accumulation layer including a SiN layer serving as a gate insulating film. In case of programming, electrons tunneled from a channel FN are accumulated in the charge accumulation layer of the memory cell. In case of erasing, the electrons accumulated in the charge accumulation layer of the memory cell are released to the channel.

Abstract: A dynamic random access memory (DRAM) and its manufacturing method are provided. The DRAM includes bit line contact structures, bit line structures, first insulating structures, a capacitor contact structure, a first connecting pad, a second insulating structure, and a capacitor structure. The bit line structure extends along a first direction. The first insulating structure extends along a second direction that intersects the first direction. The capacitor contact structure is located between two of the bit lines and two of the first insulating structures. The first connecting pad is formed on the capacitor contact structure. The second insulating structure surrounds the first connecting pad, in which the top width of the second insulating structure is greater than the bottom width thereof.

Abstract: An anti-fuse device including a substrate, a doped region, a dielectric layer, a first contact, an anti-fuse material layer, and a second contact is provided. The doped region is located in the substrate. The dielectric layer is located on the substrate and has a first opening and a second opening. The first opening and the second opening respectively expose the doped region. The first contact is located in the first opening. The anti-fuse material layer is located between the first contact and the doped region. The second contact is located in the second opening and is electrically connected to the doped region.

Abstract: A method of forming the semiconductor device is provided. The method includes following steps. A memory structure is formed over a first conductive line over a substrate and is electrically connected to the first conductive line. A sacrificial layer is formed on the memory structure. A spacer layer is formed to cover the memory structure and the sacrificial layer. A first dielectric layer is formed to cover the spacer layer. A planarization process is performed to remove a portion of the first dielectric layer. A second dielectric layer is formed on the spacer layer and the first dielectric layer. A patterning process is performed to form an opening exposing a portion of the top surface of the sacrificial layer. The sacrificial layer is removed to form a recess. A second conductive line is formed in the opening and the recess to be electrically coupled to the memory structure.

Abstract: A manufacturing method of a memory device are provided. The method includes following steps. A gate stacking structure is formed over a substrate. A first insulating layer, a second insulating layer and a mask material layer are sequentially formed over the substrate to cover the gate stacking structure. An ion implantation process is performed on the mask material layer to form a doped portion in the mask material layer. The doped portion caps on a top portion of the gate stacking structure. A first patterning process is performed on the mask material layer using the doped portion as a shadow mask to remove a bottom portion of the mask material layer extending along a surface of the substrate. A second patterning process is performed to remove the doped portion of the mask material layer and an exposed bottom portion of the second insulating layer surrounding the gate stacking structure.

Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

Abstract: A pseudo-static random access memory includes a control unit, which controls the refresh operations of the memory to be performed as many times as the number of refresh requests that are generated during a period after the first transaction ended and before a second transaction which is after the first transaction.

Abstract: A monotonic counter memory system including a counter circuit and a memory circuit is provided. The counter circuit is configured to increase a count by one in response to a clock signal and output a count value of n bits, where n is a positive integer. The memory circuit includes a plurality of memory cells. The memory circuit is configured to store the count value. The stored count value changes one bit at each input count of the clock signal, and a bit switching time of the stored count value are smaller than 2n?1 times.

Abstract: Provided is a semiconductor memory device including a plurality of memory banks. Each of the memory banks includes a first memory cell, a second memory cell, a select circuit, and a decoding circuit. The select circuit is respectively coupled to the first and second memory cells through first and second bit lines, and selects the memory cell to be operated according to a first switch signal and a second switch signal. The decoding circuit generates the first switch signal and the second switch signal according to a memory-bank select signal, a first local column select signal, and a second local column select signal.

Abstract: A dynamic sampling method and device for semiconductor manufacture are provided. The dynamic sampling method includes: generating an N-dimensional virtual image of a wafer based on a design rule and at least one of a quality control data and context data; measuring a critical pattern in the N-dimensional virtual image to generate a virtual metrology result by using a virtual metrology; determining whether the virtual metrology result is larger than a threshold; not performing a measurement on the wafer in a case that the virtual metrology result is larger than the threshold; and performing the measurement on the wafer in a case that the virtual metrology result is not larger than the threshold.

Abstract: A semiconductor device and a manufacturing method are provided. The semiconductor device includes an active region, a bit line, a capacitor contact, a conductive ring and a storage capacitor. The active region is formed in a substrate. The bit line and the capacitor contact are disposed over the substrate and electrically connected with the active region. The bit line is laterally separated from the capacitor contact, and a top surface of the bit line is lower than a top surface of the capacitor contact. An upper portion of the capacitor contact is surrounded by the conductive ring. The storage capacitor is disposed over and in electrical contact with the capacitor contact and the conductive ring.

Abstract: An electronic device and a data transmission method thereof are provided. The data transmission method includes: setting dummy data having multiple dummy bits; inserting the dummy bits of the dummy data into transmission data according to an insertion type to generate encryption data; and transmitting the encryption data to a memory device.

Abstract: A frequency detection device for a clock signal and a detection method thereof are provided. The frequency detection device includes a pulse signal generator, a sampling signal generator, a delay device, and a sampling circuit. The pulse signal generator detects a plurality of transition edges of the clock signal and generates a pulse signal according to the transition edges of the clock signal. The sampling signal generator generates a sampling signal based on a command signal according to pluses of the pulse signal. The delay device delays the command signal to generate a delayed command signal. The sampling circuit samples the delayed command signal according to the sampling signal to generate a detection result.

Abstract: A method of monitoring a semiconductor process includes the following steps. A process parameter is set to a first condition. A first process is performed to form a first film layer on a first wafer. The first film layer does not cover a wafer edge region of the first wafer. The first wafer having the first film layer is photographed by an image capturing device to obtain a first wafer image. Image recognition is performed to the first wafer image to obtain first data. Whether a position of the first film layer is offset is determined according to the first data.

Abstract: A random-number-generating circuit is provided, which includes a noise-voltage generator, a voltage-controlled oscillator, a ring oscillator, and a D flip-flop (DFF). The noise-voltage generator converts an external voltage into a noise voltage. The voltage-controlled oscillator receives the noise voltage, and generates a first clock signal according to the noise voltage. The ring oscillator generates a sampling clock signal. The DFF receives the first clock signal, and samples the first clock signal using the sampling clock signal to obtain an output digital signal, wherein the output digital signal represents a random number.

Abstract: A memory array is provided. The memory array includes multiple memory blocks, each including multiple data storage regions and multiple groups of word lines. Each group of word lines extend across one of the memory blocks. The groups of word lines are connected to multiple overlying signal lines through multiple groups of first word line contact regions in the memory blocks and multiple second word line contact regions between the memory blocks.

Abstract: Provided is a memory device, including: a substrate; a plurality of word lines, extending in a first direction, arranged in a second direction, disposed on the substrate; a dummy structure, adjacent to ends of the word lines, disposed on the substrate, wherein the dummy structure includes a main part that extends in the second direction; and a plurality of extension parts, extending in the first direction, connected to the main part, and interposed between the main part and the word lines.