Abstract: A method for forming a semiconductor structure is provided. The method includes providing a substrate with a word line region and a select gate region adjacent to each other, sequentially forming a stack layer and a hard mask layer on the substrate, and forming patterned mandrels on the hard mask layer. The method includes forming sidewall spacers on the patterned mandrels, and forming a patterned photoresist over the select gate region. The method further includes sequentially patterning the hard mask layer and the stack layer to form word lines in the word line region and a select gate in the select gate region, respectively. There is a first spacing between the word lines, and a second spacing between the select gate and the first word line of the word lines closest to the select gate. The second spacing is greater than the first spacing.

Abstract: A temperature-sensing circuit is provided, which includes: a search-control circuit, a voltage-reference circuit, a CTAT (complementary to absolute temperature) circuit, a digital-to-analog converter (DAC) circuit, a comparison circuit, and an SAR (successive approximation register) circuit. The search-control circuit generates a reference-voltage selection signal according to a plurality of control signals. The voltage-reference circuit selects a first reference voltage from a plurality of candidate reference voltages according to the reference-voltage selection signal, and provides a second reference voltage. The CTAT circuit converts the second reference voltage into a first comparison voltage. The DAC circuit converts the first reference voltage into a second comparison voltage. The comparison circuit compares the first comparison voltage and the second comparison voltage to generate a comparison-result signal.

Abstract: A semiconductor device includes a substrate, a pair of source/drain regions, a metal-containing layer, and a gate structure. The substrate includes a trench. The source/drain regions are disposed in the substrate on opposite sides of the trench. The metal-containing layer is disposed under the trench, wherein the metal-containing layer includes a metal silicide layer, and the metal-containing layer and the substrate on opposite sidewalls of the trench collectively form the channel region of the semiconductor device. The gate structure is disposed in the trench. The gate structure includes a gate dielectric layer disposed on opposite sidewalls of the trench, a buffer layer disposed on the metal-containing layer, and a gate conductive layer disposed on the buffer layer and filling in the trench.

Abstract: A block erase method for a flash memory is provided. The block erase method is to perform block erase on a block with a predetermined block size. The block erase method includes: performing an erase verification on bytes byte-by-byte in the block when performing the block erase; checking an erase step of the byte when the byte does not pass the erase verification; when the erase step of the byte exceeds a predetermined threshold value, performing the block erase with a partitioned block smaller than the predetermined block size, and returning to an erase verification stage to perform the erase verification; and when the erase step of the bytes does not exceed the predetermined threshold value, continuing to perform the block erase with the predetermined block size, and returning to the erasure verification stage to continue to perform the erase verification.

Abstract: A semiconductor memory device includes a memory unit and an error detection and correction unit. The memory unit is an OTP memory including a data memory and a check memory. The data memory is written with replacement address information detected during a redundancy repair operation and corresponding to a defective memory cell of a memory cell array. The check memory is written with check information detected during the redundancy repair operation and corresponding to the replacement address information. The error detection and correction unit performs error detection and correction on the replacement address information based on the check information. The data memory includes a unit accommodating the replacement address information. When other replacement address information and any of the replacement address information and the check information corresponding to the replacement address information are in the unit, the error detection and correction unit will not perform error detection and correction.

Abstract: A capacitor includes cup-shaped lower electrodes disposed on a substrate, a capacitor dielectric layer conformally covering inner surfaces and outer surfaces of the cup-shaped lower electrodes, and a support layer disposed between outer surfaces of the cup-shaped lower electrodes to connect the cup-shaped lower electrodes. The capacitor further includes an annealed oxide layer, which is interposed between the inner surfaces of the cup-shaped lower electrodes and the capacitor dielectric layer, and is also interposed between a portion of the outer surfaces of the cup-shaped lower electrodes and the capacitor dielectric layer. A method for forming the capacitor is also provided.

Abstract: An wafer probe device is provided, including a holder, and a probe card. The holder has a holding surface for holding a wafer. The probe card has a probing side for probing the wafer. Wherein the holder and the probe card are disposed on the ground, and the holding surface of the holder and the probing side of the probe card are perpendicular to the ground. Wherein when the holder holds the wafer to move upwardly toward the probe card into a probing position, the probed surface of the wafer is in contact with the probe card, and the probe surface is perpendicular to the ground.

Abstract: A memory apparatus, comprising: a command decoder, generating an external refresh command; a refresh skip divider, coupled to the command decoder, catching the external refresh command and outputting a divider signal; a row hammer circuit, generating a row hammer signal; and a refresh control circuit, coupled to the command decoder, the refresh skip divider and the row hammer circuit, wherein the refresh control circuit receives the external refresh command, the divider signal and the row hammer signal, and the refresh control circuit generates an internal refresh command according to the external refresh command, the divider signal and the row hammer signal.

Abstract: A method for reducing wafer edge defects is provided. The method includes providing a wafer with a central region and an edge region, forming a hard mask layer on the wafer, forming a spacer pattern on the hard mask layer, forming a photoresist layer covering the spacer pattern, performing a wafer edge treatment process on the photoresist layer to form an annular photoresist pattern, using the annular photoresist pattern as an etching mask, and sequentially transferring the exposed spacer pattern to the hard mask layer and the wafer to form a plurality of trenches in the wafer.

Abstract: A memory device includes a controller configured for initiating a program operation for a first column of memory cells which belongs to a group of memory cells; setting a verify condition which comprises a leakage current threshold during a leakage current verifying operation; performing, via a leakage current verifying circuit, a leakage current verifying operation for the first column of the memory cells by applying a negative voltage sweep to each of first remaining M?1 unselected WLs of the M WLs until finding a first negative voltage resulting in the first column of the memory cells having passed leakage current threshold; and applying the program operation for the first column of the memory cells by applying the first negative voltage to each of the first remaining M?1 unselected WLs of the M WLs and a positive bit line voltage for the N BLs.

Abstract: A memory device and a manufacturing method are provided. The memory device includes active regions defined in a semiconductor substrate by an isolation structure, wherein the active regions are arranged as an array along first and second directions, and extend along a third direction; and word lines, extending through the active regions along the second direction in the semiconductor substrate. The active regions are arranged in pairs along the second direction. The active regions in the same pair are closely adjacent to each other by a first spacing. Adjacent pairs of the active regions are separated by a greater second spacing. A featured portion of each active region below an intersecting word line has a first side closely adjacent to the other active region in the same pair by the first spacing and a second side separated from another pair of the active regions by the second spacing, and has an inclined top surface ascending from the second side to the first side.

Abstract: A method for manufacturing package structure is provided, including: providing a substrate having recesses; forming first MEMS chips on the substrate, each with a through-substrate via, and a first sensor or microactuator on the lower surface, located in one of the recesses; forming first intermediate chips on the substrate, each respectively on one of the first MEMS chips, having a through-substrate via, and including a signal conversion unit, a logic operation unit, control unit, or a combination thereof; forming second MEMS chips on the first intermediate chips, each with a through-substrate via, having a second sensor or microactuator on its upper surface, wherein the package structure includes at least one of the first sensor and the second sensor; and forming first capping plates on the second MEMS chips, each providing a receiving space for the second sensor or microactuator on the upper surface of each second MEMS chip.

Abstract: The present invention provides a delay locked loop (DLL) that can complete the process of adjusting the delay of an internal clock signal within a predetermined execution period. The DLL includes a DLL control circuit and a delay line circuit. The DLL control circuit sets the delay amount based on the phase difference between an input clock signal and an output clock signal. The delay line circuit performs a delay operation on the input clock signal according to the delay amount, thereby generating the output clock signal. The delay line circuit includes a plurality of delay units, each delay unit includes at least one delay element, and one of the delay units includes a greater number of delay elements than another delay unit.

Abstract: The disclosure describes a syndrome decoder circuit including: a syndrome computation circuit configured to receive K bits of message bits and P bits of parity bits to calculate S bits of syndrome bits; a X bits weight correction circuit configured to receive multiple sets of first number of bits of the syndrome bits and a first digits of the K bits of message bits to generate a first set of correction masks for the first digits of K bits of message bits; and a X-1 bits weight correction circuit configured to receive multiple sets of second number of bits of the syndrome bits and a second digits of the K bits of message bits to generate a second set of correction masks for the second digits of K bits of message bits. The first number is not equal to the second number.

Abstract: A DRAM including following components is provided. A bit line stack structure includes a bit line structure and a hard mask layer. The bit line structure is located on the substrate. The hard mask layer is located on the bit line structure. A dielectric layer is located on the bit line stack structure and has an opening. A contact structure is located on the substrate and includes an active region contact and a capacitor contact. The active region contact is located on the substrate. The top surface of the active region contact is exposed by the opening. The capacitor contact is located in the opening over the active region contact. An isolation layer is located between the hard mask layer and the dielectric layer and between the capacitor contact and the bit line stack structure. An etch stop layer is located between the dielectric layer and the isolation layer.

Abstract: A peripheral circuit of a memory device includes a compensation circuit, a determination circuit, and a plurality of page buffers. The compensation circuit defines a leakage current. The determination circuit is coupled to the compensation circuit, and is operated according to the leakage current. The determination circuit includes a current source, a first current mirror, a second current mirror, a potentially-qualified-bit quantity control unit, a determination circuit enable control unit, a hysteresis circuit, and a first logic unit. The page buffers include an unselected page buffer and a selected page buffer. The unselected page buffer is coupled to the compensation circuit. The selected page buffer is coupled to the determination circuit.

Abstract: The disclosure describes a syndrome decoder circuit including: a syndrome computation circuit configured to receive K bits of message bits and P bits of parity bits to calculate S bits of syndrome bits; a X bits weight correction circuit configured to receive multiple sets of first number of bits of the syndrome bits and a first digits of the K bits of message bits to generate a first set of correction masks for the first digits of K bits of message bits; and a X?1 bits weight correction circuit configured to receive multiple sets of second number of bits of the syndrome bits and a second digits of the K bits of message bits to generate a second set of correction masks for the second digits of K bits of message bits. The first number is not equal to the second number.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a sacrificial layer over the semiconductor substrate, etching the sacrificial layer to form a sacrificial pattern, etching the semiconductor substrate using the sacrificial pattern as an etching mask to form an active region of the semiconductor substrate, trimming the sacrificial pattern, and replacing the trimmed sacrificial pattern with a gate electrode.

Abstract: A semiconductor memory device according to the present invention has a memory cell array, a write-driving/bias-reading circuit, a control circuit and a sense amplifier. The control circuit outputs a VSLC (Verify Sense Load Control) signal generated according to writing data. After the write-driving/bias-reading circuit applied the writing pulse and the complementary writing pulse, the sense amplifier receives the VSLC signal and detects the current difference between two currents respectively flowing through a first data line and a second data line; the first data line and the second data line respectively connecting a true memory cell and a complementary memory cell of the selected pair of memory cell. The control circuit controls to provide the additional current to at least one of the first data line and the second data line so as to make the detected current difference meet the required margin.

Abstract: A semiconductor device and an erasing method may control a number of times an erase pulse. The erasing method of a flash memory includes the following. Multiple sacrificial memory cells in a block are programmed with different write levels first. When a selected block is erased in response to an erase command, a monitor erase pulse (R1) is applied to a well, and then the sacrificial memory cells are verified (S_EV). When the verification fails, a voltage of the monitor erase pulse is increased and then a monitor erase pulse (R2) is applied until the verification of the sacrificial memory cells passes. When the verification is passed, a normal erase pulse (Q1) is applied to the well based on a voltage of the monitor erase pulse (R2) to erase the selected block.