Abstract: Provided is a semiconductor structure including multiple pairs of target patterns, a first conductive line, and a second conductive line. Each of the pairs of target patterns includes a top pattern and a bottom pattern. The first conductive line is disposed on a first side of the pairs of target patterns. The first conductive line is electrically connected to a top pattern of a (aN+1)th pair of target patterns in the pairs of target patterns, a is a fixed integer greater than or equal to 2, and N is an integer greater than or equal to 0. The second conductive line is disposed on a second side of the pairs of target patterns opposite to the first side. The second conductive line is electrically connected to a bottom pattern of the (aN+1)th pair of target patterns in the pairs of target patterns.

Abstract: A memory device includes at least one memory cell block, a first edge block, a second edge block, multiple first sense amplifiers, and multiple second sense amplifiers. The first edge block is coupled to multiple first word lines, where at least one of the first word lines receives an enabled first word line signal. The second edge block is coupled to multiple second word lines, where at least one of the second word lines receives an enabled second word line signal. The first sense amplifiers are disposed between the first edge block and the memory cell block. The second sense amplifiers are disposed between the second edge block and the memory cell block.

Abstract: A memory-control logic, disposed in a memory circuit, is provided. The memory circuit includes a memory-cell array that is divided into a plurality of regions that include a damaged region. The memory-control logic includes a one-time-programmable (OTP) memory array, an array-control circuit, and an address-redirecting circuit. The array-control circuit programs a memory-size type of the memory-cell array, a region-failure flag corresponding to each region, and a redirecting mapping table corresponding to each region in the OTP memory array. The array-control circuit programs the redirecting mapping table corresponding to each region according to the memory-size type to direct the redirecting mapping table corresponding to each damaged region to non-repetitive good regions.

Abstract: A method of fabricating a resistive random access memory cell includes the following steps. A second sacrificial layer is formed around a patterned stacked layer. An opening passing through first conductive layers and first sacrificial layers of the patterned stacked layer is formed. A second conductive layer is formed in the opening, and the second conductive layer and the first conductive layers form a first electrode layer. The first sacrificial layers and the second sacrificial layer are removed. A variable resistance layer and an oxygen reservoir layer are formed. The oxygen reservoir layer is patterned to form a patterned oxygen reservoir layer and expose the variable resistance layer. A second dielectric layer is formed on the variable resistance layer and the patterned oxygen reservoir layer. A second electrode is formed in the second dielectric layer.

Abstract: A method of manufacturing a semiconductor device includes the following. A core material layer and a patterned mask layer are formed above a target layer. A first spacer layer is formed and a first treatment process is performed to form a treated first spacer layer. A first removal process is performed on the treated first spacer layer and the patterned mask layer to form multiple first spacers. The core material layer is patterned to form a core layer using the first spacers as a mask. A second spacer layer is formed and a second treatment process is performed to form a treated second spacer layer. A second removal process is performed on the treated second spacer layer and the core layer to form multiple second spacers. A pattern of the second spacers is transferred to the target layer to form a patterned target layer.

Abstract: A memory device includes a word line, a bit line, an active region and a bit line contact structure. The word line is disposed in the substrate, and extends along a first direction. The bit line is disposed over the substrate, and extends along a second direction. The active region is disposed in the substrate, and extends along a third direction. The bit line contact structure is disposed between the active region and the bit line. A top view pattern of the bit line contact structure has a long axis. An angle between the extending direction of this long axis and the third direction is less than an angle between the extending direction of this long axis and the first direction, and is less than an angle between the extending direction of this long axis and the second direction.

Abstract: A low-dropout regulator including a first comparator, an edge trigger, a second comparator, a third comparator, and an output stage circuit is provided. The first comparator generates a first comparison signal according to a first reference signal and an output signal. The edge trigger outputs a trigger signal according to the first comparison signal, a second comparison signal, and a third comparison signal. The second comparator generates the second comparison signal according to the output signal and a second reference signal. The third comparator generates the third comparison signal according to the output signal and a third reference signal. The output stage circuit outputs the output signal according to the first comparison signal, the second comparison signal, and the third comparison signal. The output stage circuit includes a plurality of hysteresis controllers and a plurality of power transistors. Each hysteresis controller controls a conduction state of a corresponding power transistor.

Abstract: A non-volatile memory device and a non-volatile memory erasing operation method is provided. The method includes the following. A first erasing operation is performed, including reducing a threshold voltage of each of a plurality of memory cells of the non-volatile memory through a first erasing pulse. A first verification operation is performed to confirm whether the threshold voltage of each of the memory cells is less than an erasing target voltage level. In response to at least one of the memory cells failing the first verification operation, a second erasing operation is performed. The second erasing operation includes selecting the at least one memory cell failing the first verification operation, and reducing the threshold voltage of the at least one memory cell to be less than the erasing target voltage level through a second erasing pulse.

Abstract: A semiconductor structure includes: a plurality of calibration reference features disposed on a substrate and spaced apart from each other in a first direction; and a plurality of columns of first active features and a plurality of columns of second active features respectively disposed on opposite sides of the calibration reference features, wherein each of the columns of first active features is spaced apart from each other in a second direction, each of the columns of second active features is spaced apart from each other in the second direction, and the calibration reference features, the first active features, and the second active features are disposed on the same layer and are a portion of the substrate.

Abstract: A memory apparatus embedded with a computing function and an operation method thereof are provided. The memory apparatus includes a memory array, a plurality of data flow controllers, a plurality of computation circuits, a data bus, and a control logic circuit. The memory array includes a plurality of block groups having a plurality of memory blocks. Each of the data flow controllers selects a transmission path of data of each memory block according to a corresponding one of the data flow control signals. In a computation mode, the computation circuit computes first data from the corresponding memory block. In a normal mode, second data is transmitted between the data bus and the corresponding memory block. The data flow controller transmits the first data from the corresponding memory block to the computation circuit according to the data flow control signal provided by the control logic circuit to compute the first data.

Abstract: A semiconductor memory device includes a transmission circuit and a control circuit. The transmission circuit is configured to obtain write data and transmit that into a memory cell array according to the external clock signal when the chip selection signal is asserted. The control circuit is configured to control the transmission circuit to transmit first write data into the memory cell array when the chip selection signal changes from assertion to negation during the input period of the first write data, according to the external clock signal.

Abstract: A method of forming a semiconductor structure includes forming first to third sacrificial layers on a substrate including a memory cell area and a peripheral area with a word line area. The second and third sacrificial layers in the word line area are removed to expose the top surface of the first sacrificial layer. The first sacrificial layer in the word line area and the third sacrificial layer in the memory cell area are removed. A word line dielectric layer and a first conductive layer are formed on the substrate in the word line area. The first and second sacrificial layers in the memory cell area are removed. A tunneling dielectric layer is formed on the substrate in the memory cell area. The thickness of the tunneling dielectric layer is smaller than the thickness of the word line dielectric layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure disposed on the substrate, an inter-gate dielectric layer disposed on the floating gate structure, and a control gate structure disposed on the inter-gate dielectric layer. The control gate structure includes an electrode layer disposed on the inter-gate dielectric layer, a contact layer disposed on the electrode layer, and a cap layer disposed on the contact layer. The first spacer is disposed on a sidewall of the control gate structure and covering the electrode, the contact layer and the cap layer. A bottom surface of the first spacer is positioned between a bottom surface and a top surface of the electrode layer.

Abstract: The present invention provides a stress testing circuit including a control circuit. In a test mode, the control circuit controls a supply voltage which is applied to a pre-charge circuit including transistors in a semiconductor memory device. The control circuit controls the supply voltage according to the voltage of an external power supply and the threshold voltage of the transistors included in the pre-charge circuit.

Abstract: A flash memory capable of achieving high integration and low power consumption is formed by an AND-type memory cell array, an address buffer, a row selecting/driving circuit, a column selecting circuit, an input and output circuit, and a read/write control part. A memory cell includes, for example, a charge storage layer of an ONO structure. The read/write control part performs programming and erasing by Fowler-Nordheim (FN) tunneling between the charge storage layer and a channel of a selected memory cell.

Abstract: Provided is a memory device and a method of forming the same. The method includes: providing a substrate having multiple active regions; forming a first layer stack on the substrate; patterning the first layer stack to form multiple recesses in the first layer stack; forming a liner layer on the first layer stack to cover the recesses; performing an etching process to remove a portion of the liner layer and the first layer stack below the recesses, so as to extend the recesses downward to form multiple openings, wherein the openings respectively expose the active regions; respectively forming multiple conductive structures in the openings; forming a second layer stack on the conductive structures; and patterning the second layer stack and the conductive structures to form multiple bit-line structures and bit-line contacts, respectively.

Abstract: The invention provides a memory apparatus including a memory cell array and a voltage generation circuit. The voltage generation circuit is electrically connected to the memory cell array and includes an active voltage circuit and a sensing circuit. The active voltage circuit is configured to output an operating voltage to the memory cell array when the memory apparatus is in an active mode. The sensing circuit is configured to sense the operating voltage when the memory apparatus is in a standby mode and briefly activate the active voltage circuit to pull up the operating voltage after the operating voltage drops below a threshold.

Abstract: A semiconductor memory is provided to include an adjustment circuit. The adjustment circuit sets a second period longer than a first period and adjusts time at which the last read data is output. When a chip selection signal is set to be asserted, the semiconductor memory device performs a read operation on data according to an external clock signal. The first period begins at a rising edge or a falling edge of the external clock signal and ends when the output of the last read data begins. The second period begins when the chip selection signal goes from asserted to negated and ends when the output of the last read data is complete. The external clock signal is used to read the last read data during the read operation.

Abstract: A semiconductor manufacturing apparatus and a semiconductor manufacturing method thereof are provided. Wafers are grouped into a first wafer group and a second wafer group according to alignment mark position errors of the wafers and a first threshold value. The alignment mark position errors of the first wafer group are greater than the first threshold value, and the alignment mark position errors of the second wafer group are less than or equal to the first threshold value. A feedforward position correction value is calculated according to a difference between the alignment mark position errors of the first wafer group and a reference error value. A lithography process is performed on the wafers according to the feedforward position correction value.

Abstract: Provided is an overlay mark including a first pattern and a second pattern. The first pattern includes a plurality of first strip shapes and a plurality of first dot shapes. The plurality of first strip shapes extend along a first direction and are arranged in parallel along a second direction. The plurality of first dot shapes are respectively disposed between the plurality of first strip shapes. The second pattern includes a plurality of second strip shapes and a plurality of second dot shapes. The plurality of second strip shapes extend along the second direction and are arranged in parallel along the first direction. The plurality of second dot shapes are respectively disposed between the plurality of second strip shapes.