Patents Assigned to Winbond Electronics Corp
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Patent number: 11688651Abstract: Provided is a semiconductor structure including a substrate, at least two tested structures, an isolation structure, and a short-circuit detection structure. At least two tested structures are disposed on the substrate. The at least two tested structures include a conductive material. The isolation structure is sandwiched between at least two tested structures. The detection structure includes a detecting layer, and the detecting layer is disposed on one of the at least two tested structures, so that a short circuit defect between the at least two tested structures may be identified in an electron beam detecting process, and the detecting layer includes a conductive material. A manufacturing method of the semiconductor structure and a method for detecting a short circuit of the semiconductor structure are also provided.Type: GrantFiled: March 4, 2020Date of Patent: June 27, 2023Assignee: Winbond Electronics Corp.Inventors: Hung-Ming Su, Kazuaki Takesako, Chun-Chiao Tseng
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Patent number: 11690217Abstract: Provided is a dynamic random access memory including a substrate, a gate dielectric layer, a metal filling layer, an adhesion layer, multiple work function layers, and multiple doped regions. The substrate has a trench. The gate dielectric layer is located on a sidewall and a bottom surface of the trench. The metal filling layer is located in the trench. The adhesion layer is located between the gate dielectric layer and the metal filling layer. The work function layers are located in the trench, where each work function layer is located between a sidewall of the gate dielectric layer and a sidewall of the adhesion layer. The doped regions are located in the substrate on both sides of the trench, where part of the work function layers and part of the gate dielectric layer are laterally sandwiched between part of the doped regions and part of the adhesion layer.Type: GrantFiled: July 6, 2021Date of Patent: June 27, 2023Assignee: Winbond Electronics Corp.Inventors: Shou-Chi Tsai, Chun-Lin Li
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Patent number: 11690214Abstract: A dynamic random access memory (DRAM) and its manufacturing method are provided. The DRAM includes a buried word line, a bit line, a bit line contact structure, a capacitive contact structure, and an air gap structure. The buried word line is formed in the substrate and extends along a first direction. The bit line is formed on the substrate and extends along a second direction. The bit line contact structure is formed below the bit line. The capacitive contact structure is adjacent to the bit line and surrounded by the air gap structure. The air gap structure includes a first air gap and a second air gap respectively located on a first side and a second side of the capacitive contact structure. The first air gap exposes a shallow trench isolation structure in the substrate. The second air gap exposes a top surface of the substrate.Type: GrantFiled: September 22, 2021Date of Patent: June 27, 2023Assignee: WINBOND ELECTRONICS CORP.Inventors: Hung-Yu Wei, Pei-Hsiu Peng, Wei-Che Chang
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Publication number: 20230197184Abstract: The present invention provides a memory system in which a semiconductor memory device can be accessed properly. The memory system includes a memory controller and a semiconductor memory device. The memory controller sends a command, an address, and first checking data to the semiconductor memory device. When the semiconductor memory device receives first response information that indicates that no error has been detected, it sends or receives read data or write data from the semiconductor memory device. When the semiconductor memory device receives the command, the address, and the first checking data, it uses the first checking data to detect errors in the command and the address, and sends the first reply information when no error is detected, and when no error is detected in the command and the address, it sends or receives read data or write data from the semiconductor memory device.Type: ApplicationFiled: November 15, 2022Publication date: June 22, 2023Applicant: Winbond Electronics Corp.Inventor: Takahiko SATO
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Patent number: 11683926Abstract: A method includes forming a stack of material layers to cover an array region and a periphery region of a substrate. A first patterned mask layer is formed, and the pattern of the first patterned mask layer is transferred to the stack of material layers, thereby forming a first array pattern and a first periphery pattern respectively in the array and periphery regions. A second patterned mask layer is provided above the first array and periphery patterns. The pattern of the second patterned mask is not aligned with the pattern of the first patterned mask. The pattern of the second patterned mask layer is transferred to form the first and second sacrificial patterns respectively in the array and periphery regions. The first array pattern, the first and second sacrificial patterns, and the first periphery pattern are simultaneously transferred to form a second array pattern and a second periphery pattern.Type: GrantFiled: September 15, 2021Date of Patent: June 20, 2023Assignee: WINBOND ELECTRONICS CORP.Inventors: Po-Han Wu, Pai-Chun Tsai, Tzu-Ming Ou Yang, Shu-Ming Lee
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Patent number: 11682470Abstract: A memory device including a memory cell array, a redundant fuse circuit and a memory controller is provided. The memory cell array includes multiple regular memory blocks and multiple redundant memory blocks. The redundant fuse circuit includes multiple fuse groups recording multiple repair information. Each repair information is associated with a corresponding one of the redundant memory blocks and includes a repair address, a first enable bit, and a second enable bit. The memory controller includes multiple determining circuits. Each of the multiple determining circuits generates a hit signal according to an operation address, the repair address, the first enable bit, and the second enable bit. When a target memory block is bad, and the determining circuit of the memory controller generates the hit signal, the memory controller disables the redundant memory block that is bad according to the hit signal.Type: GrantFiled: November 2, 2021Date of Patent: June 20, 2023Assignee: Winbond Electronics Corp.Inventor: Jun-Lin Yeh
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Patent number: 11683935Abstract: A NOR flash memory comprising a memory cell having a three-dimensional structure for saving power consumption is provided. The flash memory of the present invention includes a pillar part, a charge accumulating part, an insulating part, a control gate and a selecting gate. The pillar part extends in a vertical direction from a surface of a substrate and includes a conductive semiconductor material. The charge accumulating part is formed by surrounding the pillar part. The insulating part is formed by surrounding the pillar part. The control gate is formed by surrounding the charge accumulating part. The selecting gate is formed by surrounding the insulating part. One end of the pillar part is electrically connected to a bit line via a contact hole and another one end of the pillar part is electrically connected to a conductive region formed on the surface of the substrate.Type: GrantFiled: August 24, 2018Date of Patent: June 20, 2023Assignee: Winbond Electronics Corp.Inventor: Masaru Yano
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Patent number: 11682557Abstract: A recognition method for photolithography process and a semiconductor device are provided. The recognition method includes forming a mask layer on a semiconductor substrate, and then patterning the mask layer to form multiple dense line patterns in a cell region and multiple dummy dense line patterns in an interface region between the cell region and a peripheral region. At least one connection portion is provided between a first and a third dummy dense line patterns, and a second dummy dense line pattern is discontinuous at and separated from the at least one connection portion. A photoresist layer covering the peripheral region is formed on the semiconductor substrate, and whether a landing position of the photoresist layer is correct is determined according to a distance from an edge of the photoresist layer to a closest dummy dense line pattern and a width of the at least one connection portion.Type: GrantFiled: April 28, 2021Date of Patent: June 20, 2023Assignee: Winbond Electronics Corp.Inventor: Chih-Yu Chiang
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Publication number: 20230186997Abstract: The disclosure provides a semiconductor device and an erasing method that may alleviate the deterioration of a memory cell caused by ISPE. The NAND flash memory in the disclosure includes a memory cell array and an erasing component that erases selected blocks of the memory cell array. The erasing component performs a first erasing verification (EV1) and a second erasing verification (EV2) on the selected block. When the first erasing verification (EV1) passes, and the second erasing verification (EV2) fails, an erase pulse with the same erase voltage as the last time is applied, and when the first erasing verification (EV1) fails, an erase pulse with a step voltage higher than the last time is applied.Type: ApplicationFiled: November 17, 2022Publication date: June 15, 2023Applicant: Winbond Electronics Corp.Inventors: Masaru Yano, Toshiaki Takeshita
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Patent number: 11678484Abstract: Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.Type: GrantFiled: July 14, 2021Date of Patent: June 13, 2023Assignee: Winbond Electronics Corp.Inventors: Yao-Ting Tsai, Hsiu-Han Liao, Che-Fu Chuang
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Patent number: 11676662Abstract: A crossbar array apparatus suppressing deterioration of write precision due to a sneak current is provided. A synapse array apparatus includes a crossbar array configured by connecting resistance-variable type memory elements, a row selecting/driving circuit, a column selecting/driving circuit, and a writing unit performing a write operation to a selected resistance-variable type memory element. The writing unit measures the sneak current generated when applying a write voltage to a selected row line before applying the write voltage, and then the writing unit performs the write operation to the selected resistance-variable type memory element by applying a write voltage having a sum of the measured sneak current and a current generated for performing the write operation.Type: GrantFiled: July 6, 2021Date of Patent: June 13, 2023Assignee: Winbond Electronics Corp.Inventors: Yasuhiro Tomita, Masaru Yano
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Publication number: 20230178153Abstract: A memory array that includes a plurality of memory blocks and a plurality of source switches is introduced. Each of the source switches corresponds to one of the memory blocks, and each of the source switches is coupled to a common source line of the corresponding one of the memory blocks. A selected source switch, which corresponds to a selected memory block among the memory blocks for a program operation, is configured to bias the common source line of the selected memory block to a reference voltage during a program period of the program operation. An unselected source switch, which corresponds to an unselected memory block among the memory blocks for the program operation, is configured to float the common source line of the unselected memory block during the program period of the program operation.Type: ApplicationFiled: December 2, 2021Publication date: June 8, 2023Applicant: Winbond Electronics Corp.Inventor: Pil-Sang Ryoo
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Publication number: 20230178149Abstract: A resistive memory apparatus including bit lines, word lines, a memory array, bypass paths, select circuits, and a switch circuit is provided. The word lines are respectively crossed with the bit lines. The memory array includes memory elements. One end of each of the memory elements is coupled to the corresponding word line, and another end of each of the memory elements is coupled between a first node and a second node on the corresponding bit line. Each of the bypass paths is connected in parallel with the corresponding bit line between the first node point and the second node. Each of the select circuits is coupled to the corresponding bit line and bypass path, and configured to select the coupled bit line or bypass path. The switch circuit is coupled to the word lines, and configured to select one of the word lines.Type: ApplicationFiled: December 2, 2021Publication date: June 8, 2023Applicant: Winbond Electronics Corp.Inventors: Frederick Chen, Hsiu-Han Liao, Po-Yen Hsu, Chi-Shun Lin
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Publication number: 20230176750Abstract: A semiconductor memory device according to the present invention has a memory cell array, a write-driving/bias-reading circuit, a control circuit and a sense amplifier. The control circuit outputs a VSLC (Verify Sense Load Control) signal generated according to writing data. After the write-driving/bias-reading circuit applied the writing pulse and the complementary writing pulse, the sense amplifier receives the VSLC signal and detects the current difference between two currents respectively flowing through a first data line and a second data line; the first data line and the second data line respectively connecting a true memory cell and a complementary memory cell of the selected pair of memory cell. The control circuit controls to provide the additional current to at least one of the first data line and the second data line so as to make the detected current difference meet the required margin.Type: ApplicationFiled: December 7, 2022Publication date: June 8, 2023Applicant: Winbond Electronics Corp.Inventor: Hajime AOKI
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Publication number: 20230171943Abstract: Provided is a memory device including a substrate, a plurality of landing pads, a protective layer, a filling layer, a plurality of cup-shaped lower electrodes, a capacitor dielectric layer, and an upper electrode. The landing pads are disposed on the substrate. The protective layer conformally covers sidewalls of the landing pads. The filling layer is laterally disposed between the landing pads, wherein the filling layer has a top surface higher than a top surface of the landing pads. The cup-shaped lower electrodes are respectively disposed on the landing pads. The capacitor dielectric layer covers a surface of the cup-shaped lower electrodes. The upper electrode covers a surface of the capacitor dielectric layer. A method of forming a memory device is also provided.Type: ApplicationFiled: November 30, 2021Publication date: June 1, 2023Applicant: Winbond Electronics Corp.Inventors: Chung-Ming Yang, Shu-Ming Li
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Publication number: 20230170021Abstract: A semiconductor memory device capable of automatically restoring writing interrupted due to a momentary stop or a fluctuation of a power supply voltage is provided. A non-volatile memory of the disclosure includes a memory cell array formed with a NOR array and a variable resistance array. When the power supply voltage drops to a power-off level during writing into the NOR array, a reading/writing control unit writes unwritten data into the variable resistance array. Subsequently, when a power-on of the power supply voltage is detected, the reading/writing control unit reads the unwritten data from the variable resistance array and writes the unwritten data into the NOR array, so that interrupted writing is restored.Type: ApplicationFiled: October 28, 2022Publication date: June 1, 2023Applicant: Winbond Electronics Corp.Inventor: Masaru Yano
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Patent number: 11665879Abstract: A method of manufacturing a DRAM includes proving a substrate having active regions. First bit line structures are buried in the substrate. Each of first bit line structures extends along a first direction. Every two of the first bit line structures are disposed between two neighboring ones of the active regions arranged along a second direction. A plurality of pillar structures are formed arranged along the first direction by dividing each of the active regions. Second bit line structures are formed. Each of the second bit line structures is located between the pillar structures of a corresponding one of the active regions and extends through the corresponding one of the active regions along the second direction to be disposed on the first bit line structures at two sides of the corresponding one of the active regions and be electrically connected to the first bit line structures below.Type: GrantFiled: July 14, 2022Date of Patent: May 30, 2023Assignee: Winbond Electronics Corp.Inventors: Kai Jen, Hao-Chuan Chang
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Patent number: 11664435Abstract: A dynamic random access memory includes a substrate, an isolation structure, and a buried word line structure. The isolation structure is located in the substrate and defines multiple active regions. The buried word line structure is located in a word line trench in the substrate, and the word line trench passes through the active regions and the isolation structure. The buried word line structure includes a gate conductive layer, a first gate dielectric layer, and a second gate dielectric layer. The gate conductive layer is located in the word line trench. The first gate dielectric layer is located on a sidewall and a bottom surface of the word line trench. The second gate dielectric layer is located between the first gate dielectric layer and the gate conductive layer, and a top surface of the second gate dielectric layer is lower than a top surface of the gate conductive layer.Type: GrantFiled: September 2, 2021Date of Patent: May 30, 2023Assignee: Winbond Electronics Corp.Inventor: Hung-Yu Wei
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Patent number: 11664438Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a sacrificial layer over the semiconductor substrate, etching the sacrificial layer to form a sacrificial pattern, etching the semiconductor substrate using the sacrificial pattern as an etching mask to form an active region of the semiconductor substrate, trimming the sacrificial pattern, and replacing the trimmed sacrificial pattern with a gate electrode.Type: GrantFiled: November 5, 2019Date of Patent: May 30, 2023Assignee: WINBOND ELECTRONICS CORP.Inventors: Shu-Ming Lee, Yung-Han Chiu, Chia-Hung Liu, Tzu-Ming Ou Yang
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Patent number: 11665916Abstract: A memory device includes a substrate, a buried word line, a connecting structure, an air gap, and a first dielectric layer. The buried word line is disposed in the substrate. The connecting structure is disposed on the buried word line. The air gap is disposed on the buried word line and is adjacent to the connecting structure. The first dielectric layer is disposed on the connecting structure and the air gap, wherein the buried word line, the connecting structure, and the first dielectric layer are disposed in the first direction, which is substantially perpendicular to the top surface of the substrate.Type: GrantFiled: February 12, 2020Date of Patent: May 30, 2023Assignee: WINBOND ELECTRONICS CORP.Inventor: Hao Chuan Chang
