Abstract: The present invention provides a short-circuit probe card, including: a substrate having an upper surface and a lower surface; a plurality of first contacts formed on the upper surface; and a plurality of second contacts formed on the lower surface and connected to the plurality of first contacts. The first contacts and second contacts are all grounded.

Abstract: A semiconductor memory device capable of suppressing an increase in power consumption and avoiding data destruction due to the row hammer problem is provided. The semiconductor memory device includes a refresh control unit (first control unit) that sets a memory cell refresh interval based on information about a memory cell refresh interval included in a predetermined command input from the outside.

Abstract: A delay control device for controlling a delay circuit includes an oscillator, a counter, and an output control circuit. The oscillator generates an internal clock signal according to an external clock signal. The counter generates an accumulative signal according to the internal clock signal. The counter is selectively reset by the external clock signal. The output control circuit generates a delay indication signal according to the accumulative signal. The delay time of the delay circuit is adjusted according to the delay indication signal.

Abstract: A conductive bridge random access memory and its manufacturing method are provided. The conductive bridge random access memory includes a bottom electrode, an inter-metal dielectric, a resistance switching assembly, and a top electrode. The bottom electrode is disposed on a substrate, and the inter-metal dielectric is disposed above the bottom electrode. The resistance switching assembly is disposed on the bottom electrode and positioned in the inter-metal dielectric. The resistance switching assembly has a reverse T-shape cross-section. The top electrode is disposed on the resistance switching assembly and the inter-metal dielectric.

Abstract: A semiconductor memory device is provided. The semiconductor memory device can suppress increases in power consumption. As a result, damage to the data normally caused by row hammer problem can be prevented. The semiconductor memory device includes a control unit. The control unit controls a refresh operation for a memory to be performed at any interval, wherein there are a plurality of possible intervals. When read/write access to the memory is required, the control unit controls the refresh operation for the memory to be performed with a shortest interval among the intervals, until a predetermined condition is met.

Abstract: A power supply control circuit that is able to reliably discharge to the internal power supply, even when the external power supply is cut off instantaneously. The power supply control circuit includes a voltage detection unit, an internal power supply generation unit, and a control unit. The voltage detection unit detects the voltage of the external power supply. The internal power supply generation unit generates the internal power supply, according to the external power supply. The control unit controls the discharging to the internal power supply according to at least the second control signal among the first control signal and the second control signal, when the detected voltage of the external power supply drops below the predetermined value.

Abstract: A semiconductor device that can compensate for threshold fluctuations in memory cells using capacitive coupling. The flash memory includes a NAND-type memory cell array, a programing device, a reading device, and an offset voltage determining unit. The programing device programs the memory cells connected to a selected word line. The reading device reads the memory cells connected to a selected word line. The programing device programs the memory cells of a monitoring NAND string simultaneously when programing a word line. The reading device comprises a current detecting unit applying a read voltage to an unselected word line n+1, and detecting the current of the monitoring NAND string. The offset voltage determining unit determines the first and second offset voltage based on the detected current, and a reading pass voltage is applied to the unselected word line, a read voltage is applied to the selected word line.

Abstract: A semiconductor memory device can appropriately control operation timing, based on changes in the environment (for example, power supply voltage and temperature, etc.) when in use. The semiconductor memory device includes a temperature sensor 18 that detects the temperature of the semiconductor memory device, a voltage detection portion (composed of a ring oscillator 14 and a counter 15) that detects the power supply voltage of the semiconductor memory device, and a control portion 10 that controls the operation timing in the semiconductor memory device to meet specific conditions, according to the temperature detected by the temperature sensor 18 after the power is applied and the voltage detected by the voltage detection portion after the power is applied.

Abstract: A flash memory including a NAND memory cell array, a current detection unit, an offset voltage determining unit, and a reading voltage generating unit. The NAND memory cell array forms at least one monitoring NAND string in each block, which are used to monitor the cycle frequency of programing and erasing. The current detection unit detects the current that flows through the monitoring NAND string. The offset voltage determining unit determines the first offset voltage and the second offset voltage that are respectively added to the read-pass voltage and the reading voltage, according to the current detected. The reading voltage generating unit generates the read-pass voltage with the first offset voltage added. The reading voltage generating unit also generates the reading voltage with the second offset voltage added.

Abstract: A testing circuit includes a command pad, a first circuit, a second circuit, a first latch, and a second latch. The command pad receives an operation command. The first integrated circuit performs a corresponding test operation according to the operation command and an internal selection signal. The second integrated circuit performs the corresponding test operation according to the operation command and an internal selection signal. The first latch provides the operation command to the first integrated circuit according to the internal selection signal. The second latch provides the operation command to the second integrated circuit according to the internal selection signal.

Abstract: The present invention provides an oscillator circuit and a semiconductor integrated circuit, which can suppress the upper limit of the frequency of a clock signal due to an error of the constant current circuit. The oscillator circuit of the present invention includes a constant current circuit, an oscillator, and a current limiting circuit. The constant current circuit generates a first output current according to a supply voltage. The current limiting circuit receives the first output current and generates a second output current, and establishes an upper limit for the second output current when the supply voltage drops below a lower limit of a guaranteed operational range of the constant current circuit. The oscillator generates a clock signal according to the second output current. By establishing the upper limit for the second output current, the upper limit of the frequency of the clock signal can be suppressed.

Abstract: A counting method adapted to count the stage number of an integrated circuit is provided herein. The counting method includes selecting an initial segment on a graphical user interface; determining whether the initial segment is floating; when it is determined that the initial segment is coupled to a first device, storing the first device in a device register; increasing the stage number by 1 to be a first stage number corresponding to the first device; storing all segments coupled to the first device except the initial segment in a first coupling register; selecting a first segment from the first coupling register; determining whether the first segment is floating; and when it is determined that the first segment is not floating, displaying the first stage number at the first segment on the graphical user interface.

Abstract: A three-dimensional resistive memory is provided. The three-dimensional resistive memory includes a resistive switching pillar, an electrode pillar disposed within the resistive switching pillar, a stack of bit lines adjacent to the resistive switching pillar, a plurality of sidewall contacts between each of the bit lines and the resistive switching pillar, and a selector pillar extending through the stack of bit lines. The bit lines are separated vertically from each other by an insulating layer. The selector pillar contacts each of the sidewall contacts.

Abstract: A non-volatile memory device and a method thereof that are capable of improving programming speed are introduced. The non-volatile memory device includes a memory array, a charge-pump circuit, a bias detection circuit and a memory controller is introduced. The memory array includes a plurality of memory cells; and a charge-pump circuit is configured to generate a charge-pump voltage. The bias detection circuit is coupled to the charge-pump circuit and is configured to determine whether a level of the charge-pump voltage is less than a first pre-determined threshold value. The memory controller is coupled to the bias detection circuit and is configured to pause a programming operation being performed on at least one of the plurality of memory cells when the bias detection circuit determines that the level of the charge-pump voltage is less than the first pre-determined threshold value.

Abstract: A resistive random access memory device which includes a resistive random access memory array, a sense amplifier and a boosting circuit. The sense amplifier is coupled to the resistive random access memory array and is configured to sense a resistance value of the memory cell. The boosting circuit is coupled to the memory cell of the resistive random access memory array and is configured to boost a reset voltage in a boosting period of a reset period according to the resistance value of the memory cell. The boosting period is from beginning of the reset period, and the memory cell is biased with the reset voltage in the reset period to perform the reset operation. A method for a reset operation on a resistive random access memory device is also introduced.

Abstract: A dynamic random access memory including a memory cell array and a memory controller is provided. The memory cell array includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. The memory controller is coupled to the memory cells via the bit lines and the word lines. The memory controller is configured to perform a self-refresh operation on the memory cell array during a self-refresh period. Each of the bit lines includes a switch element. The memory controller controls a part of the switch elements to be conducted and a part of the switch elements not to be conducted during the self-refresh period.

Abstract: In a control method, external data input to the pseudo static random access memory with a reference clock signal in a write operation are counted to generate a first count value. Data written to a dynamic memory array of the pseudo static random access memory with a built-in clock signal in the write operation are counted to generate a second count value. An initial cycle of the built-in clock signal is smaller than a cycle of the reference clock signal. The first count value is compared with the second count value. When the first count value is equal to the second count value, a write match signal is enabled. When the enabled write match signal is received, the write operation is converted from an asynchronous mode to a synchronous mode to adjust the cycle of the built-in clock signal to be equal to the cycle of the reference clock signal.

Abstract: An operating method of a resistive memory storage apparatus includes: applying a forming voltage to a memory cell and obtaining a cell current of the memory cell; and determining whether to adjust the forming voltage and apply the adjusted forming voltage to the memory cell according to a magnitude relationship between the cell current and a reference current. The memory cell to which the forming voltage is applied operates in a heavy forming mode and serves as a one-time programmable memory device.

Abstract: The disclosure is directed to a memory device and a power reduction method of the same memory device. In an aspect, the disclosure is directed to a memory device which includes not limited to a plurality of memory banks, each having a power switch, a plurality of functional blocks for reading and writing to the plurality of memory banks and include a plurality of power switches as each functional block of the plurality of function blocks has a different power switch which turns on or turns off the functional block, a mode register circuit having a plurality of mode registers which determines whether one or more of the plurality of memory banks would maintain data storage or not, and a control logic circuit for either powering on or powering off each of the plurality of memory banks and each of the plurality of the functional blocks.

Abstract: A dynamic random access memory (DRAM) and an operation method thereof are provided. The DRAM includes a temperature sensor, a dynamic memory cell array, a control circuit, a plurality of power supply circuits and a power control circuit. The temperature sensor senses an operating temperature of the DRAM. The control circuit is coupled to a dynamic memory cell array, and accesses and manages the dynamic memory cell array. The power supply circuits powers the dynamic memory cell array and the control circuit. The power control circuit controls power outputs of the power supply circuits. When the DRAM enters the self-refresh mode, the power control circuit selectively switches between a low power control state and a normal power control state according to the operating temperature of the DRAM.