Abstract: A voltage generating device includes a low-dropout voltage regulator and a control signal generator. The low-dropout voltage regulator provides an output voltage to a power distribution network. The low-dropout voltage regulator has a feedback circuit. The feedback circuit divides the output voltage to generate a feedback voltage according to a voltage dividing ratio, and the feedback circuit sets the voltage dividing ratio according to multiple control signals. The control signal generator is coupled to the feedback circuit and the power distribution network, and generates the control signals by comparing a sensing voltage at a reference terminal of the power distribution network with multiple threshold voltages.

Abstract: A delay locked loop includes a delay line, a phase detector, a controller, an output clock generator, and a feedback circuit. The delay line receives an input clock signal and a control code, and generates a delayed clock signal by delaying the input clock signal according to the control code. The phase detector receives a reference clock signal and a feedback clock signal, and detects a phase difference between the reference clock signal and the feedback clock signal to generate phase comparison information. The controller generates the control code and a switching signal according to the phase comparison information. The output clock generator selects the delayed clock signal or an inverted signal of the delayed clock signal according to the switching signal to generate an output clock signal. The feedback circuit generates the feedback clock signal according to the output clock signal.

Abstract: A three-dimensional resistive memory is provided. The three-dimensional resistive memory includes a resistive switching pillar, an electrode pillar disposed within the resistive switching pillar, a stack of bit lines adjacent to the resistive switching pillar, a plurality of sidewall contacts between each of the bit lines and the resistive switching pillar, and a selector pillar extending through the stack of bit lines. The bit lines are separated vertically from each other by an insulating layer. The selector pillar contacts each of the sidewall contacts.

Abstract: A non-volatile memory device and a method thereof that are capable of improving programming speed are introduced. The non-volatile memory device includes a memory array, a charge-pump circuit, a bias detection circuit and a memory controller is introduced. The memory array includes a plurality of memory cells; and a charge-pump circuit is configured to generate a charge-pump voltage. The bias detection circuit is coupled to the charge-pump circuit and is configured to determine whether a level of the charge-pump voltage is less than a first pre-determined threshold value. The memory controller is coupled to the bias detection circuit and is configured to pause a programming operation being performed on at least one of the plurality of memory cells when the bias detection circuit determines that the level of the charge-pump voltage is less than the first pre-determined threshold value.

Abstract: A resistive random access memory device which includes a resistive random access memory array, a sense amplifier and a boosting circuit. The sense amplifier is coupled to the resistive random access memory array and is configured to sense a resistance value of the memory cell. The boosting circuit is coupled to the memory cell of the resistive random access memory array and is configured to boost a reset voltage in a boosting period of a reset period according to the resistance value of the memory cell. The boosting period is from beginning of the reset period, and the memory cell is biased with the reset voltage in the reset period to perform the reset operation. A method for a reset operation on a resistive random access memory device is also introduced.

Abstract: A dynamic random access memory including a memory cell array and a memory controller is provided. The memory cell array includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. The memory controller is coupled to the memory cells via the bit lines and the word lines. The memory controller is configured to perform a self-refresh operation on the memory cell array during a self-refresh period. Each of the bit lines includes a switch element. The memory controller controls a part of the switch elements to be conducted and a part of the switch elements not to be conducted during the self-refresh period.

Abstract: In a control method, external data input to the pseudo static random access memory with a reference clock signal in a write operation are counted to generate a first count value. Data written to a dynamic memory array of the pseudo static random access memory with a built-in clock signal in the write operation are counted to generate a second count value. An initial cycle of the built-in clock signal is smaller than a cycle of the reference clock signal. The first count value is compared with the second count value. When the first count value is equal to the second count value, a write match signal is enabled. When the enabled write match signal is received, the write operation is converted from an asynchronous mode to a synchronous mode to adjust the cycle of the built-in clock signal to be equal to the cycle of the reference clock signal.

Abstract: An operating method of a resistive memory storage apparatus includes: applying a forming voltage to a memory cell and obtaining a cell current of the memory cell; and determining whether to adjust the forming voltage and apply the adjusted forming voltage to the memory cell according to a magnitude relationship between the cell current and a reference current. The memory cell to which the forming voltage is applied operates in a heavy forming mode and serves as a one-time programmable memory device.

Abstract: The disclosure is directed to a memory device and a power reduction method of the same memory device. In an aspect, the disclosure is directed to a memory device which includes not limited to a plurality of memory banks, each having a power switch, a plurality of functional blocks for reading and writing to the plurality of memory banks and include a plurality of power switches as each functional block of the plurality of function blocks has a different power switch which turns on or turns off the functional block, a mode register circuit having a plurality of mode registers which determines whether one or more of the plurality of memory banks would maintain data storage or not, and a control logic circuit for either powering on or powering off each of the plurality of memory banks and each of the plurality of the functional blocks.

Abstract: A dynamic random access memory (DRAM) and an operation method thereof are provided. The DRAM includes a temperature sensor, a dynamic memory cell array, a control circuit, a plurality of power supply circuits and a power control circuit. The temperature sensor senses an operating temperature of the DRAM. The control circuit is coupled to a dynamic memory cell array, and accesses and manages the dynamic memory cell array. The power supply circuits powers the dynamic memory cell array and the control circuit. The power control circuit controls power outputs of the power supply circuits. When the DRAM enters the self-refresh mode, the power control circuit selectively switches between a low power control state and a normal power control state according to the operating temperature of the DRAM.

Abstract: A NAND flash memory suppresses an influence caused by FG coupling and has high reliability. The flash memory of the invention includes: a memory array formed with a plurality of NAND strings; a row selection unit selecting rows of the memory array; and a bit line selection circuit (200) selecting even-numbered pages or odd-numbered pages of the selected row. The even-numbered pages (BL0, BL1, BL4, BL5) include a plurality of pairs of adjacent bit line pairs, the odd-numbered pages (BL2, BL3, BL6, BL7) include a plurality of pairs of adjacent bit line pairs, and the bit lines of the even-numbered page and the bit lines of the odd-numbered page are arranged alternately.

Abstract: A volatile memory storage apparatus including a memory array, a refresh circuit and a pre-programmed circuit is provided. The memory array includes a plurality of memory banks. The refresh circuit is coupled to the memory array. The refresh circuit is configured to refresh the memory banks according to different refresh frequencies. The pre-programmed circuit is coupled to the refresh circuit. The pre-programmed circuit is configured to store the refresh frequencies. In addition, a refresh method of a volatile memory storage apparatus is also provided.

Abstract: A column decoder of a memory device includes a first selection circuit, a second selection circuit and a decoding circuit. The first selection circuit and the second selection circuit are electrically connected in cascade with a memory array of the memory device. The decoding circuit receives a column address including a first sub-address and a second sub-address. The decoding circuit generates first decoded data and second decoded data for controlling the first selection circuit and the second selection circuit based on the first sub-address and the second sub-address. A first decoder in the decoding circuit decodes the first sub-address into the first decoded data, and the first decoded data is reversed in response to change of a first predetermined bit of the second sub-address.

Abstract: Provided is a flash memory device capable of restricting power consumption in an erase operation. The invention includes a plurality of wells, a power supply device, and a coupling device. The power supply device applies erase voltages to the wells for performing an erase operation. The coupling device performs selective coupling between the wells. When performing the erase operation on the wells, the power supply device applies the erase voltage to one of the wells, and applies the erase voltage to the other one of the wells after the coupling device electrically couples the one of the wells to the other one of the wells.

Abstract: A boosting circuit, includes an output circuit including a first transmission circuit, transmitting charges of a first boosting node to a first output node according to a first transmission control signal, a detection circuit, detecting the voltage level of the first output node, and a pre-charge circuit pre-charging the first boosting node according a detection signal of the detection circuit; a first pump circuit includes a second transmission circuit, transmitting charges to a second output node according to a second transmission control signal, and a first capacitance unit, coupled to the first boosting node, boosting the voltage level of the first boosting node according to charges transmitted in the second output node; and a control circuit, coupled to the output circuit and the first pump circuit, controls the second transmission control signal according to the voltage level of the first output node.

Abstract: A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of even local bit lines and a plurality of odd local bit lines. The column decoder includes a plurality of even pass transistors, a plurality of even clamp transistors, a plurality of odd pass transistors, and a plurality of odd clamp transistors. Each of the even clamp transistors has a control terminal coupled to an even clamp line, a first terminal coupled to a respective one of the even local bit lines, and a second terminal coupled to a ground voltage. Each of the odd clamp transistors has a control terminal coupled to an odd clamp line, a first terminal coupled to a respective one of the odd local bit lines, and a second terminal coupled to the ground voltage.

Abstract: A flash memory 100 capable of reducing electric fields applied to the word lines on a memory array and reducing a chip area, includes a memory array 110, a word line decoder 120 disposed at an end of the memory array on the row direction, selecting a predetermined memory block in the memory array according to an address signal, and outputting a selecting signal to the selected memory block, and a word line drive circuit 130 comprising a switch circuit arranged between the memory arrays 110A and 110B and switching the application of the work voltage to a memory cell according to the selecting signal, and a pump circuit raising the voltage level of the selecting signal. The word line decoder 120 has lines WR(i) to transmit the selecting signals. The lines WR(i) are connected to the switch circuit of the word line drive circuit 130.

Abstract: A random access memory and a refresh controller thereof are provided. The refresh controller includes a write action detector, a latch device, a reset circuit, and a refresh masking device. The write action detector is coupled to an address decoder of the random access memory, and is used to detect a write action in an address corresponding to the address decoder and generate a detection result. The latch device is coupled to the write action detector, and is used to receive and latch the detection result. The reset circuit is coupled to the latch device, receives a reset control signal, and resets the detection result according to the reset control signal. The refresh masking device is coupled to a corresponding word line control circuit and the latch device and is used to mask a refresh action on the word line control circuit according to the detection result.

Abstract: An optical proximity correction (OPC) photomask is provided. The photomask includes two opening patterns and a pair of scattering bar patterns. The two patterns are arranged on a substrate along a first direction and separated from each other by a predetermined distance. The pair of scattering bar patterns is arranged on the substrate along a second direction perpendicular to the first direction and adjacent to two opposing sides of each opening pattern. Each scattering bar pattern does not overlap with the opening patterns on the first and second directions as viewed from a cross sectional perspective. A phase shift of 180° exists between each opening pattern and each scattering bar pattern.

Abstract: A semiconductor device and a method for fabricating the same are described. The semiconductor device includes a well of a first conductive type, first doped regions of a second conductive type, gates of the second conductive type, second doped regions of the first conductive type, and isolation structures. The well is disposed in a substrate. The first doped regions are disposed in the well. The first doped regions are arranged in parallel and extend along a first direction. The gates are disposed on the substrate. The gates are arranged in parallel and extend along a second direction different from the first direction. One of the first doped regions is electrically connected to one of the gates. Each of the second doped regions is disposed in the first doped regions between two adjacent gates. Each of the isolation structures is disposed in the substrate between two adjacent first doped regions.