Abstract: The invention includes the steps of: (1) during the 0th frame, setting value of an extend flag of zero length paging message through P-channel to be 1 for informing the portable terminal to receive the paging message within the 2nd frame; (2) during the frames of a first-type following the 2nd frame, via a data/voice field, broadcasting the information to the portable terminal.

Abstract: A method for improving sensitivity of a RF receiver and a RF receiver designed by the same are provided. The RF receiver, which receives a RF signal, comprises a sampling converting circuit, a decoding circuit, a frequency-hopping circuit, a constant current source and a ring oscillating circuit. The RF receiver outputs a frequency-hopping signal to the frequency-hopping circuit when the decoding circuit determines that the digital data converted from the RF signal is not equivalent to each of the internal preset data. The frequency-hopping circuit outputs a frequency-hopping current to the ring oscillating circuit to change a sampling clock of the RF receiver.

Abstract: A method for adjusting an executing efficiency adapted in an electronic apparatus, wherein the electronic apparatus has a central processing unit (CPU) and uses an operating system to manage data. The method includes steps of obtaining a loading value when the operating system is executed to detect the CPU under the electronic apparatus operation, and adjusting a working frequency and a working voltage of the CPU corresponding to the loading value for achieving adjustment of the executing efficiency in the electronic apparatus.

Abstract: The present invention provides a kind of contactless electromagnetic identification code IC circuit, which contains a control circuit to detect an input pad, and to provide a coding signal to decide one identification code for the contactless electromagnetic induced identification code IC. The control circuit contains: a carry clock signal source, which provides a carry clock signal to the input pad for generating a responding signal from the input pad; and a flip-flop set, which connects to the input pad, decides the identification code and forms the coding signal according to the pad's responding signal and the carry clock signal.

Abstract: A method for fabricating a capacitor comprises the steps of: forming a lower electrode of a metal over a substrate; forming a capacitor dielectric film of an oxide dielectric film on the lower electrode; depositing a metal film on the capacitor dielectric film; performing a thermal processing in a hydrogen-content atmosphere after the step of depositing the metal film; and patterning the metal film to form an upper electrode of the metal film after the step of performing the thermal processing. Thus, the adhesion between the upper electrode and the capacitor dielectric film is improved, and capacitor characteristics can be improved.

Abstract: A method and an apparatus for growing a layer on one surface of a wafer by liquid phase deposition are provided. At first, a first wafer is putted on a first wafer-holder by its first surface. Then, a growth-liquid vessel having a first opening at the bottom is mounted on the first wafer-holder. Thereafter, a growth liquid is poured into the growth-liquid vessel to expose a second surface of the first wafer to the growth liquid for growing the layer on the second surface of the first wafer. Then, the, first wafer is taken out from the first wafer-holder to obtain a wafer with a layer grown only on one surface.

Abstract: The present invention provides an electrostatic discharge-protection device located between a pad and a specific voltage point. The electrostatic discharge-protection device has a P-type substrate. Then a first N-type well, a first P-type doped region, and a first N-type doped region, are formed on the P-type substrate, wherein the first P-type doped region and the first N-type doped region are coupled to the specific voltage point, respectively. A second P-type doped region and a second N-type doped region are formed on the first N-type well and are coupled to the pad, respectively. Moreover, a third N-type doped region and a fourth N-type doped region are formed on the P-type substrate. The third N-type doped region is coupled to the pad, and a second N-type well is formed between the third N-type doped region and the fourth N-type doped region.

Abstract: In a traditional ROM semiconductor process, ROM codes are performed by ion implantation. Due to the limitations of ion implantation energy and threshold control, the implantation for program codes must be performed before forming an inter-layer oxide layer. Therefore, the required delivery time of the process becomes longer. The invention provide a method of manufacturing ROMs that can shorten delivery time by using only one mask to simultaneously form program codes and contact windows.

Abstract: A disk assembly includes an assembly housing having a front end for inserting/retrieving therethrough a disk storing thereon computer-accessible data. The front panel is mounted at the front end and has a slot for passing therethrough the disk. USB connectors are mounted on the front panel for electrically connecting therethrough a peripheral device to a computer case. The computer case can conveniently mount therein such a disk assembly.

Abstract: A method for adjusting an executing efficiency adapted in an electronic apparatus, wherein the electronic apparatus has a central processing unit (CPU) and uses an operating system to manage data. The method includes steps of obtaining a loading value when the operating system is executed to detect the CPU under the electronic apparatus operation, and adjusting a working frequency and a working voltage of the CPU corresponding to the loading value for achieving adjustment of the executing efficiency in the electronic apparatus.

Abstract: A test apparatus for testing function of a USB hub under the control of a USB host computer is provided. The USB host computer issues a USB command during the test. The test apparatus includes a USB bus, an emulation device, a standard bus and a micro-controller device. The USB bus is coupled to the USB hub. The emulation device emulates an USB device connected to the USB bus. The standard bus is connected to the USB host computer. The micro-controller device is connected to the standard bus and the emulation device respectively to process a USB transaction corresponding to the USB command. The invention provides a testing environment which is fully compliant to the WINDOWS 98 environment.

Abstract: The present invention provides an apparatus for capturing images and for manipulating a cursor. The apparatus can be used for operation in a first mode and a second mode. The apparatus includes an opto-electronic mechanism that is provided for receiving image signals. The apparatus also has a user-selectable trigger that allows a user to assert or de-assert a mode signal that determines whether operation is desired in the first mode or the second mode. The apparatus has a controller that is coupled to the opto-electronic mechanism and user-selectable trigger for receiving the mode signal. When operation is in the first mode, the received image signals are processed and used to control movement of a cursor on a screen or display. When operation is in the second mode, the received image signals are processed and displayed as video images on a PC.

Abstract: An apparatus that performs a left shift operation includes a shifter unit that contains the value to be shifted, a flag having an input coupled to the left-most bit of the shifter unit for receiving sign bit information for the value to be shifted, an overflow detector having inputs coupled to the shifter unit and the flag for determining the existence of an overflow condition, and a shift counter having outputs coupled to the shifter unit and the overflow detector.

Abstract: A SOI device structure is formed on a SOI substrate having a body contact. The SOI substrate has an insulating layer thereon and a silicon layer is disposed on the insulating layer. A gate is disposed on the silicon layer. A source region and a drain region are respectively disposed within the silicon layer beside the gate. A body contact is provided at an interface between the insulating layer and the silicon layer wherein the body contact is preferably located between the source region and the gate. The body contact, disposed between the source region and the gate can reduce kink effect and body effect, thereby enhancing the performance of device formed on SOI.

Abstract: The structure of high-Q inductor applied in a monolithic circuit according to the invention comprises a plurality of spiral metal lines and a plurality of dielectric layers, each dielectric layer formed between two adjacent spiral metal lines. Furthermore, via plugs are formed in each dielectric layer to electrically connect two adjacent spiral metal lines. A spiral air trench is formed along the spacing of the spiral metal lines in the dielectric layers. Therefore, 3D-structure of the inductor of the invention can greatly reduce the series resistance thereof without widening the spiral metal lines. In addition, the spiral air trench, filled with air which has a lower dielectric constant, can efficiently reduce the parasitic capacitance between the spacing of the spiral metal lines. As a result, the inductor of the invention has a higher quality factor at a proper RF operating frequency region.

Abstract: A fabrication method for a self-aligned contact opening involves using polysilicon to protect a cap layer above a conductive line or even a corner of a spacer on a sidewall of the conductive line. A silicon oxide layer is then etched using a conventional silicon oxide etching recipe to form a self-aligned contact opening. This conventional silicon oxide etching recipe not only has a higher etching selectivity for silicon oxide to silicon nitride, but also yields a higher etching selectivity ratio for silicon oxide to polysilicon.

Abstract: A method of retrieving storage capacity of damaged sector. A storage medium comprising a storage capacity part and a reserved capacity part is provided. The storage capacity part comprises multiple primary sectors, while the reserved capacity part comprises multiple secondary sectors. The storage medium is scanned to find and record a damaged sector in the storage capacity part. An identity field of the damaged sector is overwritten by an null identity field of one of the secondary sectors. The identity field of the damaged sector is written into the secondary sector.

Abstract: A buffer is integrated with an ESD protection circuit onto a semiconductor substrate. The ESD protection circuit is triggered by means of a MOS-like device having a first spreading resistance during an ESD event. The buffer includes a plurality of finger-type devices connected in parallel, where each finger-type device is provided with a second spreading resistance less than the first spreading resistance.

Abstract: An operation mode for waking up a system predetermined by a user is stored before the system is in standby mode. After the system is in standby mode, the peripherals and the peripheral controller are separated to prevent the peripheral controller from receiving the output signal from the peripherals. The wake-up control circuit then receives the output signal from the peripherals. In the standby mode, if the output signal from the peripherals is consistent with the user's predetermined operation mode, the system is woken up by the wake-up control circuit and returns to the normal operation mode.

Abstract: An IC package architecture with electrostatic discharge (ESD) protection is provided for use on an IC package for the purpose of allowing the ESD robustness of the IC package to be further enhanced and the structural complexity of the same to be further simplified as compared to the prior art. The IC package includes a lead frame having a die pad for mounting an IC chip thereon, a plurality of package pins with some no-connect pins which are grouped into at least one no-connect pin unit, each unit consisting of one single no-connect pin or a number of consecutively arranged no-connect pins.