Abstract: A volatile memory storage apparatus including a memory array, a refresh circuit and a pre-programmed circuit is provided. The memory array includes a plurality of memory banks. The refresh circuit is coupled to the memory array. The refresh circuit is configured to refresh the memory banks according to different refresh frequencies. The pre-programmed circuit is coupled to the refresh circuit. The pre-programmed circuit is configured to store the refresh frequencies. In addition, a refresh method of a volatile memory storage apparatus is also provided.

Abstract: A NAND flash memory suppresses an influence caused by FG coupling and has high reliability. The flash memory of the invention includes: a memory array formed with a plurality of NAND strings; a row selection unit selecting rows of the memory array; and a bit line selection circuit (200) selecting even-numbered pages or odd-numbered pages of the selected row. The even-numbered pages (BL0, BL1, BL4, BL5) include a plurality of pairs of adjacent bit line pairs, the odd-numbered pages (BL2, BL3, BL6, BL7) include a plurality of pairs of adjacent bit line pairs, and the bit lines of the even-numbered page and the bit lines of the odd-numbered page are arranged alternately.

Abstract: A column decoder of a memory device includes a first selection circuit, a second selection circuit and a decoding circuit. The first selection circuit and the second selection circuit are electrically connected in cascade with a memory array of the memory device. The decoding circuit receives a column address including a first sub-address and a second sub-address. The decoding circuit generates first decoded data and second decoded data for controlling the first selection circuit and the second selection circuit based on the first sub-address and the second sub-address. A first decoder in the decoding circuit decodes the first sub-address into the first decoded data, and the first decoded data is reversed in response to change of a first predetermined bit of the second sub-address.

Abstract: Provided is a flash memory device capable of restricting power consumption in an erase operation. The invention includes a plurality of wells, a power supply device, and a coupling device. The power supply device applies erase voltages to the wells for performing an erase operation. The coupling device performs selective coupling between the wells. When performing the erase operation on the wells, the power supply device applies the erase voltage to one of the wells, and applies the erase voltage to the other one of the wells after the coupling device electrically couples the one of the wells to the other one of the wells.

Abstract: A resistive random-access memory device includes a RRAM array including a plurality of RRAM cells coupled to a source line, a controller, a bit-line decoder, and a sense circuit. Each of the RRAM cells storing a logic state and is selected by the corresponding bit line and word line. The controller selects a selected RRAM cell by a bit-line signal and a selected word line and determines the logic state according to a sense signal. The bit-line decoder couples a data bit line to the selected bit line according to a bit-line signal. The sense circuit is coupled to the data bit line and compares a memory current flowing through the selected RRAM with a reference current to generate the sense signal. The sense circuit sinks the memory current from the data bit line when operating in a reset operation and a reverse read operation.

Abstract: A resistive random-access memory (RRAM) device and a method thereof are disclosed. The RRAM device is contains a plurality of bit cells, a plurality of word lines, a plurality of bit lines and a plurality of source lines. Each bit cell includes a transistor and resistive element, the transistor includes a gate, a source and a drain, and the resistive element is coupled to the drain of the transistor. The plurality of word lines are arranged in parallel to one another, and coupled to respective gates of the transistors. The plurality of bit lines are arranged in parallel to one another and being intersected with the plurality of word lines, and coupled to respective drains of the transistors through the resistive elements. The plurality of source lines are arranged in parallel to one another and the plurality of bit lines.

Abstract: An RRAM circuit includes word lines, bit lines, source lines, memory cells, and a sense module. Each of the memory cells includes a resistor and a transistor. The resistor alternates between a high impedance and a low impedance, and is coupled to one of the bit lines. The transistor is controlled by one of the word lines and coupled between the resistor and one of the source lines. The sense module includes a switch and a sense amplifier. The switch is controlled by an output signal and coupled to one of the bit lines. The sense amplifier compares the data voltage, which is generated by a current flowing through the switch and the resistor, and a reference voltage to generate the output signal. The switch is turned off when the data voltage exceeds the reference voltage, and is turned on otherwise.

Abstract: A boosting circuit, includes an output circuit including a first transmission circuit, transmitting charges of a first boosting node to a first output node according to a first transmission control signal, a detection circuit, detecting the voltage level of the first output node, and a pre-charge circuit pre-charging the first boosting node according a detection signal of the detection circuit; a first pump circuit includes a second transmission circuit, transmitting charges to a second output node according to a second transmission control signal, and a first capacitance unit, coupled to the first boosting node, boosting the voltage level of the first boosting node according to charges transmitted in the second output node; and a control circuit, coupled to the output circuit and the first pump circuit, controls the second transmission control signal according to the voltage level of the first output node.

Abstract: A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of even local bit lines and a plurality of odd local bit lines. The column decoder includes a plurality of even pass transistors, a plurality of even clamp transistors, a plurality of odd pass transistors, and a plurality of odd clamp transistors. Each of the even clamp transistors has a control terminal coupled to an even clamp line, a first terminal coupled to a respective one of the even local bit lines, and a second terminal coupled to a ground voltage. Each of the odd clamp transistors has a control terminal coupled to an odd clamp line, a first terminal coupled to a respective one of the odd local bit lines, and a second terminal coupled to the ground voltage.

Abstract: A flash memory 100 capable of reducing electric fields applied to the word lines on a memory array and reducing a chip area, includes a memory array 110, a word line decoder 120 disposed at an end of the memory array on the row direction, selecting a predetermined memory block in the memory array according to an address signal, and outputting a selecting signal to the selected memory block, and a word line drive circuit 130 comprising a switch circuit arranged between the memory arrays 110A and 110B and switching the application of the work voltage to a memory cell according to the selecting signal, and a pump circuit raising the voltage level of the selecting signal. The word line decoder 120 has lines WR(i) to transmit the selecting signals. The lines WR(i) are connected to the switch circuit of the word line drive circuit 130.

Abstract: A random access memory and a refresh controller thereof are provided. The refresh controller includes a write action detector, a latch device, a reset circuit, and a refresh masking device. The write action detector is coupled to an address decoder of the random access memory, and is used to detect a write action in an address corresponding to the address decoder and generate a detection result. The latch device is coupled to the write action detector, and is used to receive and latch the detection result. The reset circuit is coupled to the latch device, receives a reset control signal, and resets the detection result according to the reset control signal. The refresh masking device is coupled to a corresponding word line control circuit and the latch device and is used to mask a refresh action on the word line control circuit according to the detection result.

Abstract: An optical proximity correction (OPC) photomask is provided. The photomask includes two opening patterns and a pair of scattering bar patterns. The two patterns are arranged on a substrate along a first direction and separated from each other by a predetermined distance. The pair of scattering bar patterns is arranged on the substrate along a second direction perpendicular to the first direction and adjacent to two opposing sides of each opening pattern. Each scattering bar pattern does not overlap with the opening patterns on the first and second directions as viewed from a cross sectional perspective. A phase shift of 180° exists between each opening pattern and each scattering bar pattern.

Abstract: A semiconductor device and a method for fabricating the same are described. The semiconductor device includes a well of a first conductive type, first doped regions of a second conductive type, gates of the second conductive type, second doped regions of the first conductive type, and isolation structures. The well is disposed in a substrate. The first doped regions are disposed in the well. The first doped regions are arranged in parallel and extend along a first direction. The gates are disposed on the substrate. The gates are arranged in parallel and extend along a second direction different from the first direction. One of the first doped regions is electrically connected to one of the gates. Each of the second doped regions is disposed in the first doped regions between two adjacent gates. Each of the isolation structures is disposed in the substrate between two adjacent first doped regions.

Abstract: A method for determining native threshold voltage of nonvolatile memory includes following steps. A memory cell including a control gate, a charge storage layer, a source region, and a drain region is provided. A programming operation is performed on the memory cell by using F-N tunneling effect to obtain a programming curve of time versus threshold voltage. In the programming operation, a positive voltage is applied to the control gate. An erase operation is performed on the memory cell by using F-N tunneling effect to obtain an erasure curve of time versus threshold voltage. In the erase operation, a negative voltage is applied to the control gate. The absolute values of the positive voltage and the negative voltage are the same. The native threshold voltage of memory cell is determined from the cross point of the programming curve and the erasure curve.

Abstract: A phase change memory (PCM) in which the phase change storage element is crystallized by a gradually increasing/decreasing operating current. The PCM comprises a switching circuit, the phase change storage element, a bit select switch, a pulse generating module, and a counting module. The switching circuit comprises a plurality of switches, selectively providing branch paths to an output terminal of a current source. The bit select switch controls the conduction between the phase change storage element and the output terminal of the current source. The pulse generating module outputs a pulse signal oscillating between high and low voltage levels. When enabled, the counting module counts the oscillations of the pulse signal, and outputs the count result by a set of digital data. The set of digital data are coupled to the switching circuit to control the switches therein.

Abstract: A memory device is disclosed. A pillar structure comprises a first electrode layer, a dielectric layer overlying the first electrode layer, and a second electrode layer overlying the dielectric layer. A phase change layer covers a surrounding of the pillar structure. A bottom electrode electrically connects the first electrode layer of the pillar structure. A top electrode electrically connects the second electrode layer of the pillar structure.

Abstract: A phase change memory device is disclosed, including a substrate. The phase change memory also includes a bottom electrode. A conductive structure with a cavity is provided to electrically contact the bottom electrode, wherein the conductive structure includes sidewalls with different thicknesses. A phase change spacer is formed to cross the sidewalls with different thicknesses. A top electrode is electrically contacted to the phase change spacer.

Abstract: A channel sharing method and device thereof are disclosed. The method starts by providing a plurality of channels, wherein each of the channels comprises a time interval. A time slot having a width being X times of a maximum value of all the time intervals is provided, wherein C is a positive number. Each of the channels is generated by a permutation of at least one repeat time, which is M times of the width of the time slot, wherein M is an integer larger than 0. A first time slot of the repeat time comprises a signal. A maximum time span of the signals in each channel is the time interval of each channel. All the channels are arranged so that at least one of the signals in each channel is not collided with the signals of other channels in a worst time delay.

Abstract: A phase-change memory is provided. The phase-change memory comprises first and second electrodes, wherein the first and second electrodes comprise phase-change material. A conductive path is formed between the first and second electrodes and electrically connects the first and second electrodes, wherein the conductive path comprises an embedded metal layer and a phase-change layer resulting in current from the first electrode to the second electrode or from the second electrode to the first electrode passing through the embedded metal layer and the phase change layer.

Abstract: A protection circuit protects an integrated circuit (“IC”) from peak voltages and includes a voltage divider coupled to a silicon controlled rectifier. The voltage divider allows for adjustment of the trigger voltage, trigger current, and holding voltage of the protection circuit so that the protection circuit can conduct current after a particular voltage level has been applied to the protection circuit without accidental triggering on by, for example, noise.