Abstract: A serial communication method and system is provided for use with a battery management system. The system includes a port capable of sending and receiving pulses over a single conductor, serial interface logic compatible with a serial protocol and capable of generating and detecting signals on the port and communicating the signals with an internal bus in the battery management system wherein each signal in the serial protocol is defined by a specific number of pulses. In the serial protocol, a zero signal corresponds to a sequence of two pulses, a one signal corresponds to a sequence of three pulses, an acknowledge signal corresponds to a sequence of four pulses, and a start signal corresponds to a sequence of five pulses.

Abstract: A method and apparatus for setting a floating gate in a floating gate circuit using dual conduction of Fowler-Nordheim tunnel devices is disclosed. In one embodiment, the present invention comprises a floating gate circuit having a single floating gate. During a set mode, the charge level on the floating gate is modified until it is set to a predetermined charge level that is a function of an input set voltage. In another embodiment, the floating gate circuit comprises two floating gates. During a set mode the charge level on each of the floating gates is modified until the difference in charge level between the two floating gates is a predetermined function of an input set voltage that is capacitively coupled to one of the floating gates during the set mode.

Abstract: An integrated, programmable, feed forward current controller supplies a control current to control or compensate a drive current used to drive a device having a response that depends upon a physical parameter such as temperature. Control current compensation data are stored in a programmable look-up table as a function of the physical parameter. A transducer converts a measurement of the physical parameter into an electrical signal that is digitized and used to address the contents of the look-up table. The compensated control current stored in the look-up table is converted into an analog current and used to control or compensate a drive current used to drive the device under control, thereby minimizing the dependence of the device's response on the physical parameter.

Abstract: An apparatus for using feedback to set a floating gate to a desired voltage during a set mode is disclosed. The apparatus includes a floating gate, a first and second tunnel device formed respectively between the floating gate and a first and second electrode, a first circuit coupled to the floating gate for comparing the voltage on the floating gate to a third voltage and for generating an output voltage at an output terminal, and a feedback circuit coupled between the output terminal and the floating gate. The feedback circuit includes the first tunnel device and a third tunnel device for causing the floating gate voltage to be modified as a function the output voltage until the floating gate voltage, the third voltage and the output voltage are approximately equal.

Abstract: Methods and apparatus for converting analog signals to digital signals using a switched integrator. A method includes receiving the analog signal at a summing junction, receiving a clock signal transitioning between a first level and a second level, connecting an output of the summing junction to an integrator when the clock signal is at the first level, and disconnecting the output of the summing junction from the integrator when the clock signal is at the second level. An output signal is provided, and is determined by the polarity of an output of the integrator when the clock signal transitions from the first level to the second level. The output signal is delayed, and received with a digital-to-analog converter; which provides an output to the summing junction.

Abstract: A method for sensing the voltage on a floating gate in a floating gate circuit during a set mode is disclosed.

Abstract: A bias controller includes a bias detector, a reference comparator, a memory component, and a reference voltage. The bias detector is operable to detect a bias current associated with a device controlled by the bias controller and produce a proportional sensed bias voltage. The reference comparator is operable to compare the bias voltage to a reference voltage and produce a first control signal operable to adjust a bias output of the bias controller. The memory component stores a plurality of reference voltage settings, one for each mode of operation of the device, the memory component including a mode setting input and a reference voltage output signal. The reference voltage adjustment circuit adjusts the reference voltage applied to the reference comparator in accordance with the mode of the device as controlled by the reference voltage output signal.

Abstract: Methods and apparatus for adjusting DC bias of a radio frequency (RF) amplifier for changing operating conditions such as multiple modulation techniques when no RF is present. A digitally controlled voltage source is programmed to maintain the amplifier bias. The voltage source can be a digitally controlled potentiometer. The amplifier's DC output current can be converted to a voltage and compared to a programmable reference representative of the optimal amplifier bias. The comparator output determines a direction to drive the voltage source. A digital clock is enabled to drive the voltage source when no RF is present. Alternatively, the amplifier's output current can be read by a processor that determines the optimal bias. The bias can be written to a data register that sets the voltage on the voltage source. The system automatically compensates for changes in the amplifier's optimal bias due to aging, temperature, and modulation scheme.

Abstract: Disclosed are solid-state potentiometers having high resolution and high accuracy. An exemplary potentiometer comprises a first main terminal, a second main terminal, a wiper terminal, and a resistor stack comprising a plurality M of resistors coupled in series to one another at a plurality of M−1 internal nodes. Each of the resistors in the stack has substantially the same value of RS ohms. The potentiometer further comprises a first variable resistance network coupled between one end of the resistor stack and the potentiometer's first main terminal, and a second variable resistance network coupled between the other end of the resistor stack and the potentiometer's second main terminal. The first variable resistance network has a variable resistance value R1 which varies between zero ohms and RP ohms. The second variable resistance network has a variable resistance value R2 which is maintained substantially at value of (RP−R1).

Abstract: An integrated power and sense device provides a current used in measuring the charge of a rechargeable battery. The charge measurement apparatus for a rechargeable battery powered system includes an integrated power and sense device having a power device and a sense device, connected to the rechargeable battery and a load; the sense device operatively coupled to provide a mirror current that is a fixed ratio of the current in the power device, and a first circuit that uses the mirror current to measure the charge in the rechargeable battery.

Abstract: A battery management system is provided having a battery management unit (BMU) and an integrated switch and sense device (SSD) for accurately measuring the charge state of a rechargeable battery and providing charge protection for the rechargeable battery. The system includes a load, a integrated power and sense device including a power device and a sense device, the integrated power and sense device connected between the rechargeable battery and the load wherein the sense device provides a mirror current proportional to the current in the power device, a first circuit that measures the rechargeable battery current using the mirror current, and a second circuit that measures the charge in the rechargeable battery using the mirror current.

Abstract: Disclosed are solid-state potentiometers having high resolution and high accuracy. An exemplary potentiometer has a first main terminal, a second main terminal, a wiper terminal, and a resistor stack having a plurality M of resistors coupled in series to one another at a plurality of M−1 internal nodes. Each of the resistors in the stack has substantially the same value of RS ohms. The potentiometer further has a first variable resistance network coupled between one end of the resistor stack and the potentiometer's first main terminal, and a second variable resistance network coupled between the other end of the resistor stack and the potentiometer's second main terminal. The first variable resistance network has a variable resistance value R1 which varies between zero ohms and RP ohms. The second variable resistance network has a variable resistance value R2 which is maintained substantially at value of (RP−R1).

Abstract: A battery management system is provided having a battery management unit (BMU) and an integrated switch and sensor unit (SSU) for accurately measuring the charge state of a rechargeable battery and providing charge protection for the rechargeable battery. The system uses a charger unit to charge the rechargeable battery and a combination sensor switch circuit having a first and second mirror current proportional to the current used to charge and discharge the rechargeable battery. The switch function in sensor switch circuit disconnects the battery from receiving additional charge when a disconnect signal is provided. A battery management unit is used to detect conditions such as over voltage, over current, and over temperature associated with the rechargeable battery and transmit the disconnect signal to the sensor and switch unit when at least one condition is detected.

Abstract: A compact, electrically-erasable and electrically-programmable nonvolatile memory device employing novel programming and erasing techniques and using two layers of conductive or semiconductive material is disclosed. The memory cell of the present invention comprises a first layer serving as a floating gate and a second layer serving the functions of erasing the floating gate and of selecting the device for reading and programming the floating gate. The second layer may be made common to more than one memory device of the present invention. Programming of the device occurs by tunneling electrons into the first layer (floating gate) by hot-electron injection from a channel region controlled by the second layer. In one preferred embodiment of the present invention, erasure of the memory cell occurs by causing the tunneling of electrons from the first layer (floating gate) to the second layer by an enhanced tunneling mechanism.

Abstract: An apparatus and method for depositing a tunneling oxide layer between two conducting layers utilizing a low pressure, low temperature chemical vapor depostion (LPCVD) process is disclosed wherein tetraethylorthosilicate (TEOS) is preferably used. As applied to an electrically erasable programmable read only memory (EEPROM) device having polysilicon layers, the apparatus is constructed by forming a first layer of polysilicon, patterned as desired. A layer of silicon dioxide is then deposited by decomposition of TEOS to form the tunneling oxide to a predetermined thickness. If enhanced emission structures are desired, a layer of relatively thin tunneling oxide may be grown on the first layer of polysilicon. The oxide layer is then annealed and densified, preferably using steam and an inert gas at a specific temperature. A second layer of polysilicon is then formed on top of the tunneling oxide.

Abstract: A compact, electrically-erasable and electrically-programmable nonvolatile memory device employing novel programming and erasing techniques and using two layers of conductive or semiconductive material is disclosed. The memory cell of the present invention comprises a first layer serving as a floating gate and a second layer serving the functions of erasing the floating gate and of selecting the device for reading and programming the floating gate. The second layer may be made common to more than one memory device of the present invention. Programming of the device occurs by tunneling electrons into the first layer (floating gate) by hot-electron injection from a channel region controlled by the second layer. In one preferred embodiment of the present invention, erasure of the memory cell occurs by causing the tunneling of electrons from the first layer (floating gate) to the second layer by an enhanced tunneling mechanism.

Abstract: A wireless communication system for communicating between a host system and a stand-alone device through an electromagnetic coupling medium is disclosed. The communication system has the capabilities of bi-directional data communications between the host and the stand-alone device and of powering the stand-alone device with energy pulses coupled through the electromagnetic coupling medium from the host. The electromagnetic medium is capable of supporting the bi-directional flow of energy pulses and energy transitions thereof between the host and stand-alone device. In one embodiment, bi-directional communication is provided by transmitting and detecting predetermined numbers of consecutive energy transitions coupled through the medium. Resting durations immediately precede and follow each predetermined number of consecutive energy transitions.

Abstract: A compact, electrically-erasable and electrically-programmable nonvolatile memory device employing novel programming and erasing techniques and using two layers of conductive or semiconductive material is disclosed. The memory cell of the present invention comprises a first layer serving as a floating gate and a second layer serving the functions of erasing the floating gate and of selecting the device for reading and programming the floating gate. The second layer may be made common to more than one memory device of the present invention. Programming of the device occurs by tunneling electrons into the first layer (floating gate) by hot-electron injection from a channel region controlled by the second layer. In one preferred embodiment of the present invention, erasure of the memory cell occurs by causing the tunneling of electrons from the first layer (floating gate) to the second layer by an enhanced tunneling mechanism.

Abstract: A wireless communication system for communicating between a host system and a stand-alone device through an electromagnetic coupling medium is disclosed. The communication system has the capabilities of bi-directional data communications between the host and the stand-alone device and of powering the stand-alone device with energy pulses coupled through the electromagnetic coupling medium from the host. The electromagnetic medium is capable of supporting the bi-directional flow of energy pulses and energy transitions thereof between the host and stand-alone device. In one embodiment, bi-directional communication is provided by transmitting and detecting predetermined numbers of consecutive energy transitions coupled through the medium. Resting durations immediately precede and follow each predetermined number of consecutive energy transitions.

Abstract: An apparatus and method for depositing a tunneling oxide layer between two conducting layers utilizing a low pressure, low temperature chemical vapor deposition (LPCVD) process is disclosed wherein tetraethylorthosilicate (TEOS) is preferably used. As applied to an electrically erasable programmable read only memory (EEPROM) device having polysilicon layers, the apparatus is constructed by forming a first layer of polysilicon, patterned as desired. A layer of silicon dioxide is then deposited by decomposition of TEOS to form the tunneling oxide to a predetermined thickness. If enhanced emission structures are desired, a layer of relatively thin tunneling oxide may be grown on the first layer of polysilicon. The oxide layer is then annealed and densified, preferably using steam and an inert gas at a specific temperature. A second layer of polysilicon is then formed on top of the tunneling oxide.