Abstract: Low power consumption methods and apparatus for distributing and controlling on-chip generated high voltage, for programming nonvolatile memory arrays and the like.

Abstract: Integrated circuit high voltage ramp rate control methods and devices which provide a controllable ramp rate action. The systems are particularly useful for "on-chip" EEPROM high voltage power supplies.

Abstract: A compact, floating gate, nonvolatile, electrically-alterable memory device fabricated with three layers of polysilicon and a substrate coupling electrode is described. A particular form of the device utilizes asperities to promote tunnel current flow through relatively thick oxides by means of relatively low average applied voltages. The use of four electrode layers leads to an extremely dense cell and memory array configuration. The substrate electrode is used to establish bias voltages in the cell.

Abstract: An integrated testing apparatus provides bidirectional coupling of a high voltage either from an internal source on an integrated circuit to a first external pin on the integrated circuit package, or to the output point of said internal source of high voltage from a voltage source external to the integrated circuit package that is coupled to said first external pin, said coupling occurring in response to an enabling signal externally impressed on a second external pin on said integrated circuit package. The testing apparatus is substantially transparent to normal integrated circuit operation when said enabling signal is removed from said second external pin.

Abstract: An integrated circuit system for generating a regulated high voltage tunneling pulse whose voltage level varies as a function of the voltage level needed to initiate tunneling of electrons across one or more dielectric gaps between respective first and second regions. The voltage level of initial electron tunneling is compared with a predetermined voltage margin so as to cause said generated tunneling voltage pulse to have a voltage level equal to the sum of said detected tunneling voltage and said voltage margin. The tunneling voltage pulse is then maintained substantially at this level for a predetermined duration before the tunneling pulse is discharged.

Abstract: Nonvolatile, integrated metal-oxide semiconductor random access memory systems utilizing integrated floating gate circuit elements, and integrated means for the generation and control of high voltages in the provision of self-contained, nonvolatile electrically-alterable static RAM circuit systems.

Abstract: Integrated circuit system for generating a rise-time regulated and level controlled high voltage pulse utilizing a plurality of diode-connected stages driven by capacitively coupled low voltage clocks. The maximum output voltage may be controlled by a gated diode reference device, which provides a reference voltage independent of power supply voltage. A feedback circuit may be provided which controls the high voltage rise time by modulating the effective low voltage clock amplitude driving the high voltage generator. A MOS logic level interface circuit may also be provided for sensing achievement of the predetermined high voltage level.

Abstract: A compact, floating gate, nonvolatile, electrically-alterable memory device fabricated with four layers of polysilicon is described. A particular form of the device utilizes asperities to promote tunnel current flow through relatively thick oxides by means of relatively low average applied voltages. The use of four electrode layers leads to an extremely dense cell and memory array configuration.

Abstract: Nonvolatile, semiconductor random access memory cells comprising a static, RAM cell and a nonvolatile memory element which may be interconnected with the static random-access memory cell by capacitative coupling, such that the RAM cell contents may be directly copied to the nonvolatile element, and such that the nonvolatile memory cell contents will be copied to the RAM cell upon applying power to the RAM cell. The nonvolatile memory element may be a substrate-coupled floating gate cell incorporating self-regulated and asperity enhanced tunnel currents.

Abstract: Nonvolatile semiconductor electrically-alterable, floating-gate memory methods and devices which utilize substrate coupling for self-regulated, tunnel-current-shaping to provide improved device characteristics. The substrate coupling also facilitates the cell interconnection to other circuit elements.

Abstract: Nonvolatile, integrated metal-oxide semiconductor random access memory systems utilizing integrated floating gate circuit elements, and integrated means for the generation and control of high voltages in the provision of self-contained, nonvolatile electrically-alterable static RAM circuit systems.