Patents Assigned to Xilinx, Inc.
  • Patent number: 11327677
    Abstract: An integrated circuit (IC) can include a decomposer data mover circuit configured to read sub-arrays from array data stored in a source memory; generate metadata headers for the sub-arrays, wherein each metadata header includes location information indicating location of a corresponding sub-array within the array data; create data tiles, wherein each data tile includes a sub-array and a corresponding metadata header; and output the data tiles to compute circuitry within the IC. The IC can include a composer data mover circuit configured to receive processed versions of the data tiles from the compute circuitry; extract valid data regions from the processed versions of the data tiles; and write the valid data regions to a destination memory based on the location information from the metadata headers of the processed versions of the data tiles.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: May 10, 2022
    Assignee: Xilinx, Inc.
    Inventors: Kristof Denolf, Jack S. Lo, Kornelis A. Vissers
  • Patent number: 11330738
    Abstract: An electronic device is provided that balances the force applied to temperature control elements such that stress within components of the electronic device can be effectively managed. In one example, an electronic device is provided that includes a printed circuit board (PCB), a chip package, a thermal management system, a thermal spreader, and first and second biasing members. The chip package is mounted to the PCB. The thermal management system and spreader are disposed the opposite of the chip package relative to the PCB. The first biasing member is configured to control a first force sandwiching the chip package between the thermal spreader and the PCB. The second biasing member is configured to control a second force applied by the thermal management system against the thermal spreader. The first force can be adjusted separately from the second force so that total forces applied to the chip package and PCB may be effectively balanced.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: May 10, 2022
    Assignee: XILINX, INC.
    Inventors: Gamal Refai-Ahmed, Chi-Yi Chao, Huayan Wang, Suresh Ramalingam, Volker Aue
  • Patent number: 11327836
    Abstract: Some examples herein provide for protection of data on a data path in a memory system in an integrated circuit. In an example, an integrated circuit includes a bit checker circuit, an Error Correcting Code (ECC) encoder circuit, an ECC decoder circuit, and a check bit generation circuit. The bit checker circuit is configured to check write data based on write-path check bit(s). The ECC encoder circuit is configured to generate a write encoded ECC value based on the write data. The write encoded ECC value is to be written to the memory with the write data. The ECC decoder circuit is configured to decode a read encoded ECC value and check read data based on the read encoded ECC value. The read encoded ECC value and read data are read from the memory. The check bit generation circuit is configured to generate read-path check bit(s) from the read data.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: May 10, 2022
    Assignee: XILINX, INC.
    Inventors: Danny Tsung-Heng Wu, David Tran
  • Patent number: 11329665
    Abstract: Disclosed approaches for performing a Burrows-Wheeler transform (BWT) of a sequence of data elements, S, include determining sets of less-than values and sets of equal-to values for the data elements. Index values are determined for the data elements based on the sets of less-than values. Each index value indicates a count of data elements of S that a data element is lexicographically greater than. Rank values are determined for the data elements of S based on the sets of less-than values and the sets of equal-to values. Each rank value indicates for the data element an order of the data element in the BWT relative to other ones of the data elements of equal value. Positions in the BWT of S for the data elements are selected based on the index values and rank values, and the data elements are output in the order indicated by the respective positions in the BWT.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: May 10, 2022
    Assignee: XILINX, INC.
    Inventors: Mohammad Saifee Dohadwala, Raghukul B. Dikshit
  • Patent number: 11327899
    Abstract: An example programmable integrated circuit (IC) includes a processing system having a processor, a master circuit, and a system memory management unit (SMMU). The SMMU includes a first translation buffer unit (TBU) coupled to the master circuit, an address translation (AT) circuit, an AT interface coupled to the AT circuit, and a second TBU coupled to the AT circuit, and programmable logic coupled to the AT circuit in the SMMU through the AT interface.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: May 10, 2022
    Assignee: XILINX, INC.
    Inventors: Ygal Arbel, Sagheer Ahmad, Gaurav Singh
  • Publication number: 20220138140
    Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Applicant: Xilinx, Inc.
    Inventors: Sonal Santan, Ravi N. Kurlagunda, Min Ma, Himanshu Choudhary, Manjunath Chepuri, Cheng Zhen, Pranjal Joshi, Sebastian Turullols, Amit Kumar, Kaustuv Manji, Ravinder Sharma, Ch Vamshi Krishna
  • Patent number: 11323391
    Abstract: Some examples described herein relate to multi-port stream switches of data processing engines (DPEs) of an electronic device, such as a programmable device. In an example, a programmable device includes a plurality of DPEs. Each DPE of the DPEs includes a hardened processor core and a stream switch. The stream switch is connected to respective stream switches of ones of the DPEs that neighbor the respective DPE in respective ones of directions. The stream switch has input ports associated with each direction of the directions and has output ports associated with each direction of the directions. For each direction of the directions, each input port of the input ports associated with the respective direction is selectively connectable to one of the output ports associated with the respective direction.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: May 3, 2022
    Assignee: XILINX, INC.
    Inventors: Peter McColgan, David Clarke, Goran Hk Bilski, Juan J. Noguera Serra, Baris Ozgul, Jan Langer, Tim Tuan
  • Patent number: 11321150
    Abstract: A method and data processing system are provided. The data processing system comprises an application associated with a plurality of sockets and a sub-system for making data available to the application via the plurality of sockets. The sub-system is configured to provide in response to a request from the application: an indication of events that have occurred on one or more of the plurality of sockets; and an indication of an order in which the events should be processed.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: May 3, 2022
    Assignee: Xilinx, Inc.
    Inventors: Steven Leslie Pope, David James Riddoch, Kieran Mansley, Sian Cathryn James
  • Patent number: 11323108
    Abstract: A low current line termination circuit includes first and second input interfaces each configured to receive a Vreceive+ and a Vreceive? voltage, respectively. The circuit further includes a first diode connected transistor (“DCT”) coupled to the second input interface, a first switching transistor (“ST”) coupled to the first DCT and to the first input interface, and a first delay element coupled between one of the input interfaces and a gate of the first ST. The circuit further includes a second DCT coupled to the one of the two input interfaces, a second ST coupled to the second DCT and to the second input interface, and a second delay element coupled between another of the two input interfaces and a gate of the second ST.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 3, 2022
    Assignee: XILINX, INC.
    Inventors: Bob W. Verbruggen, Christophe Erdmann, Ionut C. Cical
  • Patent number: 11314277
    Abstract: Examples described herein provide a method for reducing lane-to-lane serial skew in an integrated circuit. In an example using a processor-based system, a maximum clock skew is determined from clock skews of respective lanes of a transmitter of the IC. Each of the clock skews corresponds to a skew of a clock signal of the respective lane relative to a same reference clock signal. A skew match amount is determined for each lane of the lanes of the transmitter. The skew match amount for a respective lane of the lanes is based on the maximum clock skew and the clock skew of the respective lane. Configuration data is generated to configure the transmitter to shift incoming data for each lane of the lanes based on the skew match amount for the respective lane.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: April 26, 2022
    Assignee: XILINX, INC.
    Inventors: Riyas Noorudeen Remla, Gourav Modi, Azarudin Abdulla, Chee Chong Chan
  • Patent number: 11314911
    Abstract: High-level synthesis implementation of data structures in hardware can include detecting, within a design and using computer hardware, a data structure and a compiler directive for the data structure. The design may be specified in a high-level programming language. Using the computer hardware and based on the compiler directive, a modified version of the design may be created by, at least in part, generating a modified version of the data structure based on the compiler directive. Using the computer hardware, a circuit design may be generated from the modified version of the design by creating, at least in part, a hardware memory architecture for the circuit design and mapping the modified version of the data structure onto the hardware memory architecture.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: April 26, 2022
    Assignee: Xilinx, Inc.
    Inventors: Fangqing Du, Sheng Wang, Alain Darte, Alexandre Isoard, Hem C. Neema, Lin-Ya Yu
  • Patent number: 11315858
    Abstract: A chip package assembly having robust solder connections are described herein. In one example, a chip package assembly is provided that includes an integrated circuit (IC) die and a package substrate. Solder pads are arranged to connect to pillars of the IC die via solder connections. Solder resist in the corners of the package substrate and surrounding the solder connections may be inhibited from cracking isolating the portion of the solder resist surrounding the solder pads and/or by providing an offset between centerlines of the pillars and solder pads.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: April 26, 2022
    Assignee: XILINX, INC.
    Inventors: Yu Hsiang Sun, Suresh Ramalingam, Tien-Yu Lee, Jaspreet Singh Gandhi
  • Patent number: 11308572
    Abstract: Methods and systems for invisible watermarking of images and video are disclosed. According to one embodiment, a method for watermarking video comprises selecting a block corresponding to a subset of pixels in a video frame. The block has quantized coefficients generated during encoding of the block. A modification function is applied to a candidate quantized coefficient (QC) in the block to incorporate a bit of a watermark message. The modification function is based on a set of configuration parameters.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: April 19, 2022
    Assignee: Xilinx, Inc.
    Inventor: Jack Benkual
  • Patent number: 11301295
    Abstract: Implementing an application using a plurality of data processing engines (DPEs) can include, in a first pass, mapping, using computer hardware, a data flow graph onto an array of DPEs by minimizing direct memory access (DMA) circuit usage and memory conflicts in the array of DPEs and, in response to determining that a mapping solution generated by the first pass requires an additional DMA circuit not specified by the data flow graph, inserting, using the computer hardware, additional buffers into the data flow graph. In a second pass, the additional buffers can be mapped, using the computer hardware, onto the array of DPEs by minimizing the memory conflicts in the array of DPEs.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: April 12, 2022
    Assignee: Xilinx, Inc.
    Inventors: Shail Aditya Gupta, Rishi Surendran
  • Patent number: 11303911
    Abstract: Methods and systems for storing pixels of a video/image frame are disclosed. According to one embodiment, a method for storing pixels of a video frame comprises allocating a region of a memory to a pixel block having pixels of the video frame selected in out-of-raster-scan-order. The allocated region corresponds to a plurality of contiguous locations in the memory, and wherein the allocated region includes a first portion for storing pixel values. Values of pixels are stored in the pixel block in the first portion.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: April 12, 2022
    Assignee: Xilinx, Inc.
    Inventor: Michael Scott
  • Patent number: 11302674
    Abstract: A chip package assembly and method for fabricating the same are provided that provide a modular chip stack that can be matched with one or more chiplets. The use of chiplets enables the same modular stack to be utilized in a large number of different chip package assembly designs, resulting much faster development times at a fraction of the overall solution cost.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: April 12, 2022
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Suresh Ramalingam, William E. Allaire, Hong Shi, Kerry M. Pierce
  • Patent number: 11296707
    Abstract: An integrated circuit can include a data processing engine (DPE) array having a plurality of tiles. The plurality of tiles can include a plurality of DPE tiles, wherein each DPE tile includes a stream switch, a core configured to perform operations, and a memory module. The plurality of tiles can include a plurality of memory tiles, wherein each memory tile includes a stream switch, a direct memory access (DMA) engine, and a random-access memory. The DMA engine of each memory tile may be configured to access the random-access memory within the same memory tile and the random-access memory of at least one other memory tile. Selected ones of the plurality of DPE tiles may be configured to access selected ones of the plurality of memory tiles via the stream switches.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: April 5, 2022
    Assignee: Xilinx, Inc.
    Inventors: Javier Cabezas Rodriguez, Juan J. Noguera Serra, David Clarke, Sneha Bhalchandra Date, Tim Tuan, Peter McColgan, Jan Langer, Baris Ozgul
  • Patent number: 11294992
    Abstract: An example hardware accelerator for a computer system includes a programmable device and further includes kernel logic configured in a first programmable fabric of the programmable device, a shell circuit configured in a second programmable fabric of the programmable device, the shell circuit configured to provide an interface between a computer system and the kernel logic, and an intellectual property (IP) checker circuit in the kernel logic The IP checker circuit is configured to obtain a device identifier (ID) from the first programmable fabric and a signed whitelist, the signed whitelist including a list of device IDs and a signature, verify the signature of the signed whitelist, compare the device ID against the list of device IDs, and selectively assert or deassert an enable of the kernel logic in response to presence or absence, respectively, of the device ID in the list of device IDs and verification of the signature.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: April 5, 2022
    Assignee: XILINX, INC.
    Inventors: Brian S. Martin, Premduth Vidyanandan, Mark B. Carson, Neil Watson, Gary J. McClintock
  • Patent number: 11295000
    Abstract: An accelerator card can include a read-only memory configured to store a security identifier in a designated field therein and a satellite controller configured to read the security identifier in response to a reset event. The satellite controller is configured to select, based on the security identifier, a security mode from a plurality of security modes and implement the selected security mode in the accelerator card.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: April 5, 2022
    Assignee: Xilinx, Inc.
    Inventors: Dmitriy Shtalenkov, Krishnakumar Sugumaran, Maurice Penners
  • Publication number: 20220100840
    Abstract: An accelerator card can include a read-only memory configured to store a security identifier in a designated field therein and a satellite controller configured to read the security identifier in response to a reset event. The satellite controller is configured to select, based on the security identifier, a security mode from a plurality of security modes and implement the selected security mode in the accelerator card.
    Type: Application
    Filed: September 28, 2020
    Publication date: March 31, 2022
    Applicant: Xilinx, Inc.
    Inventors: Dmitriy Shtalenkov, Krishnakumar Sugumaran, Maurice Penners