Abstract: Mining proxy acceleration may include receiving, within a mining proxy, packetized data from a mining pool server and determining, using the mining proxy, whether the packetized data qualifies for broadcast processing. In response to determining that the packetized data qualifies for broadcast processing, the packetized data can be modified using the mining proxy to generate broadcast data. The broadcast data can be broadcast, using the mining proxy, to a plurality of miners subscribed to the mining proxy.

Abstract: Systems and methods for designing an information processing system are described. In one embodiment, a design space is partitioned into a plurality of independent partitions based on a defined set of rules. A unique processing core is assigned to each partition. A plurality of starting points is generated for each partition, where each starting point is associated with a machine learning algorithm. The starting points for each partition may include a performance driven seed and an area-driven seed. A set of feasible designs associated with the information processing system are determined.

Abstract: A circuit arrangement includes an array of MAC circuits, wherein each MAC circuit includes a cache configured for storage of a plurality of kernels. The MAC circuits are configured to receive a first set of data elements of an IFM at a first rate. The MAC circuits are configured to perform first MAC operations on the first set of the data elements and a first one of the kernels associated with a first OFM depth index during a first MAC cycle, wherein a rate of MAC cycles is faster than the first rate. The MAC circuits are configured to perform second MAC operations on the first set of the data elements and a second one of the kernels associated with a second OFM depth index during a second MAC cycle that consecutively follows the first MAC cycle.

Abstract: Some examples described herein provide for an on-die virtual probe in an integrated circuit structure for measurement of voltages. In an example, an integrated circuit comprises a voltage-controlled frequency oscillator circuitry and a processor circuitry. The voltage-controlled frequency oscillator circuitry comprises a plurality of circuitry components and is configured to generate a signal having a frequency related to a supply voltage. The voltage-controlled frequency oscillator circuitry is disposed at a location of the integrated circuit proximal to the supply voltage being monitored. The processor circuitry is configured to identify a relationship between the frequency of the signal and the supply voltage. The processor circuitry is also configured to determine a value of the supply voltage associated with the signal based on the identified relationship. The processor circuitry further monitors on-die transient voltages at the location of the integrated circuit based on the value of the supply voltage.

Abstract: Disclosed circuits and methods involve a first register configured to store of a first convolutional neural network (CNN) instruction during processing of the first CNN instruction and a second register configured to store a second CNN instruction during processing of the second CNN instruction. Each of a plurality of address generation circuits is configured to generate one or more addresses in response to an input CNN instruction. Control circuitry is configured to select one of the first CNN instruction or the second CNN instruction as input to the address generation circuits.

Abstract: Implementing a hardware description language (HDL) memory includes determining, using computer hardware, a width and a depth of the HDL memory specified as an HDL module for implementation in an integrated circuit (IC), partitioning, using the computer hardware, the HDL memory into a plurality of super slices corresponding to columns and the plurality of super slices into a plurality of super tiles arranged in rows. A heterogeneous memory array may be generated, using the computer hardware. The heterogeneous memory array is formed of different types of memory primitives of the IC. Input and output circuitry configured to access the heterogeneous memory array can be generated using the computer hardware.

Abstract: In disclosed approaches of neural network processing, a host computer system copies an input data matrix from host memory to a shared memory for performing neural network operations of a first layer of a neural network by a neural network accelerator. The host instructs the neural network accelerator to perform neural network operations of each layer of the neural network beginning with the input data matrix. The neural network accelerator performs neural network operations of each layer in response to the instruction from the host. The host waits until the neural network accelerator signals completion of performing neural network operations of layer i before instructing the neural network accelerator to commence performing neural network operations of layer i+1, for i?1. The host instructs the neural network accelerator to use a results data matrix in the shared memory from layer i as an input data matrix for layer i+1 for i?1.

Abstract: A network interface device has an input configured to receive data from a network. The data is for one of a plurality of different applications. The network interface device also has at least one processor configured to determine which of a plurality of available different caches in a host system the data is to be injected by accessing to a receive queue comprising at least one descriptor indicating a cache location in one of said plurality of caches to which data is to be injected, wherein said at least one descriptor, which indicates the cache location, has an effect on subsequent descriptors of said receive queue until a next descriptor indicates another cache location. The at least one processor is also configured to cause the data to be injected to the cache location in the host system.

Abstract: Embodiments herein describe error interceptors disposed along a bus that communicatively couples first and second circuits for redirecting in-band errors. That is, the error interceptors can block (or mask) in-band errors so they are not forwarded along the bus. Further, the error interceptors can redirect those errors such that they are converted into out-of-band errors. Moreover, the user can select which error interceptors to activate (e.g., block and redirect the errors) and which to deactivate (e.g., permit the in-band errors to pass). In this manner, the user can control which circuits receive in-band errors and which do not based on whether those circuits can handle the in-band errors.

Abstract: Disclosed approaches for generating vector codes include inputting tensor processing statements. Each statement specifies an output variable, an initial variable, and multiply-and-accumulate (MAC) operations, and each MAC operation references the output variable, elements of a first tensor, and one or more elements of a second tensor. The MAC operations are organized into groups, and the MAC operations in each group reference the same output variable and have overlapping references to elements of the first tensor. For each group of MAC operations, at least one instruction is generated to load elements of the first tensor into a first register and at least one instruction is generated to load one or more elements of the second tensor into a second register. For each group of MAC operations, instructions are generated to select for each MAC operation in the group for input to an array of MAC circuits, elements from the first register and one or more elements from the second register.

Abstract: A match-action circuit includes one or more conditional logic circuits, each having an input coupled to input header or metadata of a network packet, and each configured to generate an enable signal as a function of one or more signals of the header or metadata. Each match circuit of one or more match circuits is configured with response values associated with key values. Each match circuit is configured to conditionally lookup response value(s) associated with an input key value from the header or metadata in response to the enable signal from a conditional logic circuit. One or more action circuits are configured to conditionally modify, in response to states of the response value(s) output from the match circuit(s), data of the header or the metadata.

Abstract: Apparatus and associated methods relate to providing a machine learning methodology that uses the machine learning's own failure experiences to optimize future solution search and provide self-guided information (e.g., the dependency and independency among various adaptation behavior) to predict a receiver's equalization adaptations. In an illustrative example, a method may include performing a first training on a first neural network model and determining whether all of the equalization parameters are tracked. If not all of the equalization parameters are tracked under the first training, then, a second training on a cascaded model may be performed. The cascaded model may include the first neural network model, and training data of the second training may include successful learning experiences and data of the first neural network model. The prediction accuracy of the trained model may be advantageously kept while having a low demand for training data.

Abstract: Some examples described herein relate to multi-chip devices. In an example, a multi-chip device includes first and second chips. The first chip includes a power supply circuit and a logic circuit. The first and second chips are coupled together. The second chip is configured to receive power from the power supply circuit. The second chip includes a programmable circuit, a pull-up circuit, and a detector circuit. The detector circuit is configured to detect a presence of a power voltage on the second chip and responsively output a presence signal. The power voltage on the second chip is based on the power from the power supply circuit. The logic circuit is configured to generate a pull-up signal based on the presence signal. The pull-up circuit is configured to receive the pull-up signal and configured to pull up a voltage of a node of the programmable circuit responsive to the pull-up signal.

Abstract: Data is received at a buffer used by a protocol processing stack which protocol processes the received data. The received data is made available to, for example, an application, before the protocol processing of the data is complete. If the protocol processing is successful, the data made available to the application is committed.

Abstract: Disclosed methods and systems involve, prior to mapping logic of the module to a target integrated circuit (IC) technology, estimating total delay of a module of a circuit design and determining whether or not the module is timing critical based on the total delay of the module and a timing constraint. Also prior to mapping, the module is restructured for timing optimization in response to determining that the module is timing critical. In response to determining that the module is not timing critical, and prior to mapping, the module is restructured for area optimization. The elements of the module are then mapped to the circuit elements of the target IC technology, followed by place-and-route and generating implementation data for making an IC that implements the circuit design.

Abstract: Implementing an asymmetric memory having random port ratios using memory primitives can include detecting, using computer hardware, a hardware description language (HDL) random access memory (RAM) within a circuit design. The HDL RAM is asymmetric. Using computer hardware, a number of a plurality of memory primitives needed to implement the HDL RAM as a RAM circuit are determined based on a maximum port width ratio of the memory primitives defined as 1:N and a port width ratio of the HDL RAM defined as 1:M, wherein each of M and N is an integer and a power of two and M exceeds N. The RAM circuit is asymmetric. Using the computer hardware, a write circuit and/or a read circuit can be generated for a first port of the RAM circuit. Further, using the computer hardware, a write circuit and/or a read circuit can be generated for a second port of the RAM circuit.

Abstract: A data processing system being configured to select between different hardware resources for the running of an application configured for the sending and receiving of data over a network. The selection of hardware resources may be between resources on the network interface device, and hardware resources on the host. The selection of hardware resources may be between first and second hardware resources on the network interface device. An API is provided in the data processing system that responds to requests from the application irrespective of the hardware on which the application is executing.

Abstract: Controlling functionality of a core on a per-instance basis can include implementing, within an accelerator, an instance of a core by configuring the accelerator using configuration data, receiving, within the instance of the core, encrypted authorization data for the instance of the core, generating, using control circuitry of the instance of the core, decrypted authorization data for the instance of the core by decrypting the encrypted authorization data using a core instance identifier stored in a first control register of the instance of the core, and writing the decrypted authorization data to a second control register in the instance of the core, wherein the instance of the core enables core functionality therein based on the decrypted authorization data in the second control register.

Abstract: Apparatus and associated methods relate to determining a natural exponent from a digital word input by splitting the digital word, and retrieving a precalculated and predetermined value from a data store at an address defined by the first word. In an illustrative example, the retrieved value may be a hyperbolic sum. The hyperbolic sum may be multiplied by the second word. The hyperbolic sum may be scaled, and summed with the multiplication result to generate a scaled exponential value. The scaled exponential value may be scaled to produce an exponential value representing eX. In various examples, the digital word input may be in a fixed point or a floating point format, or converted therebetween. In various embodiments, the data store may be a lookup table. Various examples may provide a compact and versatile architecture for determining a natural exponent with minimized hardware resources.

Abstract: An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.