Abstract: The present invention provides a new method to handle power and ground signals in modular design of programmable logic devices. During module implementation, the power and ground signals of each module are associated with area constraint properties. When performing routing in the module implementation phase, the power and ground signals together with regular local signals of the module are routed in accordance with their respective area constraint properties. However, the area constraint properties of the power and ground signals are removed during assembly phase while the area constraint properties of the local signals are retained.

Abstract: Interface logic is disclosed. The interface logic comprises a first address decoder, a first set of mode logic coupled to the address decoder and a first selector coupled to the first set of mode logic. The interface logic is adaptable to connect the programmable logic to the system interconnect via one of a plurality of access modes supported by the system interconnect.

Abstract: Method and apparatus for regulating voltage within an integrated circuit is described. For example, a voltage regulator receives a first reference voltage and produces a regulated voltage. A comparator includes a first input for receiving a second reference voltage and a second input for receiving the regulated voltage. The comparator includes an offset voltage. The comparator produces a control signal indicative of whether the difference between the second reference voltage and the regulated voltage is greater than a predetermined offset voltage. A clamp circuit clamps the regulated voltage to the second reference voltage in response to the control signal. In another example, the clamp circuit is removed and a multiplexer selects either a first reference voltage or a second reference voltage to be coupled to a voltage regulator. The multiplexer is controlled via output of a comparator that compares the first reference voltage and the second reference voltage.

Abstract: A supporting structure is wafer-bonded to the upper face side of a partially or fully processed device wafer. The device wafer includes a transistor having a well region that extends into the substrate material of the device wafer. The source and drain regions of the transistor extend into the well region. After attachment of the supporting structure, the device wafer is thinned from the back side until the bottom of the well region is reached. To reduce source and drain junction capacitances, etching can continue until the source and drain regions are reached. In one embodiment, all of the well-to-substrate junction is removed in a subsequent etching step, thereby reducing or eliminating the well-to-substrate junction capacitance of the resulting transistor. Resistance between the well electrode and the transistor channel is reduced because the well contact is disposed on the back side of the device wafer directly under the gate of the transistor.

Abstract: A method for customization of the software of an FPGA-based SoC includes the steps of selecting (380) a system component used for customizing the FPGA-based SoC, configuring (382) the selected system component with parameters for use with the FPGA-based SoC and propagating (384) the parameters used to configure the selected system component to peer system components. The method further includes the step of configuring (388) the peer system components using the propagated parameters during customization of the FPGA-based SoC and creating (401) a software interface to the selected system components and to the peer system components.

Abstract: A method and apparatus for implementing fast sum-of-products logic in a Field Programmable Gate Array (FPGA) is disclosed. The method includes literal-sharing decomposition of the sum-of-products logic to reduce the number of configurable logic block (CLB) slices required to implement wide fan-in logic functions on an FPGA. The decomposition is performed by combining product terms having similar literal patterns. The apparatus includes a CLB including a plurality of slices and a second-level logic (separate from the slices) circuit to combine the outputs of the slices. Typically, the second-level logic is an OR gate or its equivalent that implements the sum portion of the sum-of-products expression. Alternatively, a combining gate may be included within the slice to combine the output of the slice to output of another slice preceding the first slice.

Abstract: Method and apparatus for recognizing data path structures in a netlist. The stages in the netlist are identified. Each stage includes a set of components that process multiple bits. The buses that connect the stages are also identified. A graph is generated to represent the stages and buses. The vertices in the graph represent the stages and the edges represent the buses. The graph is divided into subgraphs having terminating vertices that represent memory elements. Each subgraph represents a data path structure.

Abstract: A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.

Abstract: A programmable logic device, such as a field programmable gate array, is partially reconfigured using a read-modify-write scheme that is controlled by a processor. The partial reconfiguration includes (1) loading a base set of configuration data values into a configuration memory array of the programmable logic device, thereby configuring the programmable logic device; (2) reading a first frame of configuration data values from the configuration memory array; (3) modifying a subset of the configuration data values in the first frame of configuration data values, thereby creating a first modified frame of configuration data values; and (4) overwriting the first frame of configuration data values in the configuration memory array with the first modified frame of configuration data values, thereby partially reconfiguring the programmable logic device. The steps of reading, modifying and overwriting are performed under the control of a processor.

Abstract: The present invention provides a hardware breakpoint unit for a multibus, processor-based, configurable circuit. The multi-bus breakpoint unit connects to and allows tracing of multiple busses and includes the ability to break on the occurrence of a pre-determined bus event on any one of the multiple busses. The multi-bus breakpoint unit can be connected to and programmed by a host debugging system via a port on the target chip.

Abstract: A programmable logic device includes a non-volatile permission memory block to enable a customer to utilize a proprietary core. In one embodiment, the core supplier designs its core to check for a specified permission bit or bit pattern in the permission memory block before the core will operate. If the permission bit or bit pattern is set properly, the core functions correctly when implemented in the PLD. If not, the core will not function. To prevent the customer from modifying the core such that it no longer depends upon the permission bits to function, the configuration bitstream used to program the PLD can be encrypted before and during transmission to the PLD. This encryption ensures security of the customer's logic design as well as the supplier's core design. In this manner, the customer remains dependent upon properly set permission memory bits, i.e. proper authorization, to obtain core functionality.

Abstract: Methods and systems are provided for dynamically compressing and decompressing a data stream in a manner that facilitates hardware implementation. In one aspect, a compression system identifies literal data sequences of variable length in the data stream and characterizes each literal sequence with an indicator that is inserted into the data stream. Sequences that repeat previous sequences in the data stream are identified and replaced with codes characterizing the repeating sequence. Another aspect provides a decompression method and system for removing indicators inserted by the compression system and replacing codes in the data stream with the repeating sequences characterized by the codes.

Abstract: A clock divider circuit that adds little additional delay on the clock path. Each rising and falling edge of an input clock signal triggers a pulse from a pulse generator circuit. These pulses are passed to a control circuit. True and complement versions of the input clock signal are provided to a multiplexer circuit. Under the direction of the control circuit, the multiplexer circuit passes selected rising edges of the true clock signal, and selected falling edges of the complement clock signal, to an output clock terminal of the clock divider circuit. When neither the true nor the complement clock signal is passed by the multiplexer, a keeper circuit retains the value already present at the output clock terminal.

Abstract: An IC package provides structural rigidity to a flexible substrate, but still allows access to mounted capacitors after package assembly. In a flip chip package, the IC die is mounted face down on a flexible laminate substrate. A metal lid is mounted above and in contact with the die. The metal lid includes openings over portions of an outer region of the substrate to accommodate the capacitors. However, portions of the metal lid extend to the corners of the substrate to provide structural rigidity to the flexible substrate. Some embodiments are directed to packages configured as described above, but in which an IC die has yet to be mounted.

Abstract: Described are methods and circuits for identifying defective device layers and localizing defects. Production PLD tests extract statistically significant data relating failed interconnect resources to the associated conductive metal layer. Failure data thus collected is then analyzed periodically to identify layer-specific problems. Test circuits in accordance with some embodiments employ interconnect resources heavily weighted in favor of specific conductive layers to provide improved layer-specific failure data. Some such test circuits are designed to identify open defects, while others are designed to identify short defects.

Abstract: A transistor with ballast resistor formed between the transistor drain and the drain contact is formed by masking regions of the ballast resistor to increase resistivity and thus reduce required area. The invention achieves this without introducing any additional process or masking steps. Thus the invention allows a reduction in IC die size for the same ESD requirement or allows better ESD protection for a given die size.

Abstract: Method and apparatus for providing a controlled voltage to an integrated circuit is described. A first frequency value indicative of a first voltage is compared to a second frequency value indicative of a second voltage. The second frequency value is adjusted by the second voltage until the second frequency value is within a range of the first frequency value. Additionally, the second voltage may be adjusted to maintain the second frequency value within the range.

Abstract: In a plurality of logical device driver instances, each instance (201) representing a specific version (220) of the device driver, can be accessed by an embedded application (200) via a common interface (205). A logical device driver instance includes the common interface which includes a plurality of functions (206-209) linked to the embedded application. A logical device driver also includes a virtual function table (211) having pointers (212-215) that points from each of the plurality of functions of the common interface to a plurality of functions (221-224) of a specific version of the device driver among a plurality of versions of the device driver. The virtual function table is set up dynamically during run-time initialization of a logical device driver instance.

Abstract: Described are systems and methods for quickly and accurately determining the set-up and hold-time requirements and clock-to-out delays associated with sequential logic elements on programmable logic devices. Programmable interconnect resources are configured to deliver signals to the data and clock terminals of each logic element under test. One or more variable delay circuits precisely place edges of the test signals on the elements of interest while a tester monitors the data clocked into the logic element to determine whether the logic element functions properly. This process is repeated for a number of selected delays.

Abstract: Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity most of the time, and high speed during writing to the memory cell. Alternatively, inductors coupled between inverters of a latch may be used.