Abstract: A power on reset (POR) generator circuit includes a modified bandgap POR circuit in series with a modified RC POR circuit. During a fast or slow power up, the circuit behaves like a traditional bandgap POR circuit, providing a POR signal when the voltage on an internal node rises higher than a reference voltage. During a fast power up, the capacitor on the bandgap output signal ensures that the POR signal remains active long enough to reset the associated circuitry. During a slow power up, the capacitor prevents glitches in the bandgap output from being passed to the POR output signal. A feedback pulldown optionally included in the bandgap portion of the circuit helps to prevent glitches from reaching the POR output signal by raising the voltage on the internal node after the reference voltage is exceeded. Various embodiments include programmable logic devices and systems that include the described circuits.

Abstract: The present invention allows preloading of channel context in advance of actual channel change in a digital communication system. The system uses a channel identification signal to identify the present channel number of data on a data bus. Before the actual change in channel, a future channel number is inserted into the channel identification signal. Another signal is used to indicate the location of the future channel number in the channel identification signal. As a result, the system is able to know in advance the new channel number. The corresponding context can be loaded before the arrival of the new channel data.

Abstract: A one-dimensional wavelet system and method. In various embodiments, computation engines are set forth for forward and inverse transforms in a wavelet system. The computation engine includes a plurality of register banks having input ports arranged to receive input sample values and a multiplexer coupled to the output ports of the register banks. A processing unit is configured to perform the forward or inverse wavelet transform for data values that are sequenced through the register banks and multiplexer by a control unit. The computation unit is adaptable to implement discrete wavelet transform, discrete wavelet packet, and custom wavelet trees.

Abstract: A phase locked loop having a voltage-controlled oscillator is adjusted to compensate for process variations in the formation of the phase locked loop. In each instance of the phase locked loop, the center frequency of the voltage-controlled oscillator is adjusted using a bias signal while holding the control voltage of the voltage-controlled oscillator at zero. Then, the control voltage of the voltage-controlled oscillator is set to a different value and the gain of the voltage-controlled oscillator is adjusted.

Abstract: A method for testing packaged integrated circuits (ICs) having bent or broken leads. A lower portion of each lead is cut to leave a stub located close to the package body of the damaged IC. The damaged IC is then mounted onto a probe card having upward-facing probes that contact the lead stubs. Test signals are then transmitted between an IC tester and the damaged IC through the probe card.

Abstract: A system and method are provided for replacing dedicated external termination resistors typically used to implement an asymmetrical unidirectional bus I/O standard with programmable resistances that are dynamically selected by programming output driver circuits having digitally controlled impedances.

Abstract: A voltage of an input analog signal (105 or 405) can be converted to a signal whose frequency is dependent upon the analog input signal (135 or 435). A frequency divider (115 or 415) can be configured to convert the frequency dependent signal to a frequency divided signal (140 or 440). A first frequency detector (420a) or time detector (120a) can be configured to determine the frequency of the frequency divided signal, thereby creating a first output signal (145a or 445a). A second frequency detector (420b) or time detector (120b) can be configured to determine the frequency of the frequency dependent or non-frequency divided signal, thereby creating a second output signal (145b or 445b). The first and second output signals can be post-processed to generate a digital output signal (130 or 430) that is representative of the input analog signal.

Abstract: The invention provides methods for marking packaged ICs. In a first embodiment, only the minimum performance information is first marked on the package, regardless of the actual performance of the IC. This method avoids a second marking step for all ICs sold as low-performance ICs. In another embodiment, only one inking and curing step is required for all ICs. According to this method, all specified performances are marked on the packaged IC at the first marking. The IC is then tested to determine the actual performance, and all performance markings not applicable to the IC are removed, preferably with a laser. Alternatively, all applicable performance markings are identified (e.g., underlined or enclosed with a laser marking).

Abstract: Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. The reduced logic blocks are arranged in a similar layout to the original CLBs so that timing relationships remain similar in the RFPGA and FPGA. The actual timing of the RFPGA can be modified by increasing or decreasing the timing delay on various signal paths based on the FPGA design or additional timing constraints. To reduce the time required to generate RFPGAs, a database can be used to contain configurable logic block models and the corresponding reduced logic block models.

Abstract: A system and method for designing schematic diagrams of electronic circuits is provided. A library of electronic components represented in graphical form are selectable by a user for inclusion into a schematic diagram. The components are connected together to define a circuit that performs a function. In order to simulate and test a particular portion of the circuit rather than the entire circuit, the present invention provides a disabling routine that disables portions of the circuit not to be included in the simulation. The present invention allows a circuit designer/tester to focus on desired areas of a circuit while ignoring others.

Abstract: A computer implemented apparatus and method that automates the entry, modification, analysis, and generation of test benches from electrical circuits, both of which are specified as hardware description language (HDL) files. The computer implemented-method and apparatus also provides a unique mechanism that blends entry and display of timing requirements that must be met by the electric circuit.

Abstract: An inductive amplifier having a feed forward boost is provided, thereby improving the gain of the inductive amplifier at frequencies greater than 1 GigaHertz. The inductive amplifier includes a feed-forward boost circuit coupled to intermediate nodes of an inductive amplifier circuit, whereby the feed-forward boost circuit generates boost currents that are added to the currents of the inductive amplifier circuit. In one embodiment, the feed-forward boost circuit includes a boost current supply, a first boost transistor coupled between the current supply and a first intermediate node of the inductive amplifier circuit, and a second boost transistor coupled between the current supply and a second intermediate node of the inductive amplifier circuit. In one embodiment, the first and second boost transistors and the inductive amplifier circuit are controlled by the same differential input signals.

Abstract: Programmable circuit structures having reduced susceptibility to single event upsets. A circuit structure includes a programmable circuit controlled by a group of memory cells, of which at most one has an enable value. The memory cells are coupled together such that if any one memory cell in the group is at the enable value, then all other memory cells in the group are forced to a disable value. If a single event upset occurs at any of the disabling memory cells the value in the memory cell does not change, because the memory cell is being held disabling by the one enabling memory cell. However, if a single event upset occurs at the enabling memory cell, causing it to become disabling, a circuit error occurs. Thus, the susceptibility of the circuit structure has been reduced by a factor of (N−1)/N, where N is the number of memory cells.

Abstract: A configurable logic block for a programmable logic device includes a storage element having a latch clocked by a write strobe pulse. The storage element uses a write strobe signal and, optionally, a hold signal already present in the CLB. In one embodiment, the CLB includes a function generator, a write strobe generator providing hold and write strobe signals to the function generator, and a storage element driven by the function generator output signal and by the hold and write strobe signals from the write strobe generator. Because the CLB already includes a write strobe generator, it is not necessary to design additional logic to avoid race conditions in the storage element.

Abstract: A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal silicide layers stacked over a similarly shaped gate oxide. When a programming voltage is applied across the metal silicide layer, there is intense localized heating. The heating causes segregation of the channel dopant atoms towards the source and drain regions, lowering the threshold voltage of the device. The heating causes carrier activation in the polysilicon layer and dopant penetration through the oxide layer into the channel region, thereby increasing the threshold voltage of the device.

Abstract: A lookup table (LUT) for a field programmable gate array (FPGA) is designed to operate reliably at low voltage levels. The low-voltage LUT uses CMOS pass gates instead of unpaired N-channel transistors to select one memory cell output as the LUT output signal. Therefore, no voltage drop occurs across the pass gates. While this modification significantly increases the overall gate count of the LUT, this disadvantage can be mitigated by removing the half-latches required in current designs, and by removing initialization circuitry made unnecessary by the modification. Some embodiments include a decoder that decreases the number of pass gates between the memory cells and the output terminal, at the cost of an increased delay on the input paths that traverse the decoder.

Abstract: Method and system for testing circuitry of a programmable logic device (PLD). A host data processing arrangement is configured with a run-time reconfiguration programming interface, and a run-time reconfiguration test program that invokes methods of the interface executes on the host arrangement. In response to a method of the programming interface invoked from the test program, the PLD is configured with a first configuration bitstream. State data are then read back from the PLD in response to a method of the programming interface invoked from the test program. The test program also identifies differences between the state data and expected-results data.

Abstract: Method and apparatus for signal reflection removal, such as echo cancellation, is described. Signal samples are delayed. The delays allow burst processing of consecutive samples of transmitting and receiving signals in a communication network, such as in a telephone communication system. As a result, there is tremendous reduction of memory bandwidth when compared to conventional sample-by-sample processing of signals. Echo cancellers described herein can be implemented in an FPGA. Echo in over a thousand channels can be cancelled using an FPGA and an external memory device. In embodiments for reflected signal cancellation, multiple stages of echo estimation are used.

Abstract: FPGAs that contain at least one localized defect may be used to implement some designs if the localized defect is not used in the designs. To determine if the FPGA is suitable to implement a design, the design is loaded into the FPGA. The FPGA is tested to determine whether it can execute the design accurately even with the localized defect. The FPGA will be marked as suitable for that design if it passes the test. If the FPGA is found to be unsuitable for one design, additional designs may be tested. Thus, a FPGA manufacturer can sell FPGAs that are normally discarded. As a result, the price of these FPGAs could be set significantly low.

Abstract: A configuration memory array for a programmable logic device includes an array of configuration memory cells arranged in rows and columns. Initially, each of the configuration memory cells is reset to a reset state. Each row of configuration memory cells is coupled to a corresponding data line and data line driver. During configuration, each data line driver drives a configuration data value having a first state or a second state onto the corresponding data line. A configuration data value having the first state has a polarity that tends to flip the reset state of a configuration memory cell. A repeater cell is connected to an intermediate location of each data line. Each repeater cell improves the drive of configuration data values having the first state.