Abstract: A method and apparatus for placing output signals having different voltage levels on output pins of a programmable logic device (PLD). The PLD includes a plurality of function blocks (FBs), and each FB includes one or more output pins. The output signals are organized into logical output banks (LOBs), the output signals in each LOB having a common voltage level. Each of the FBs is associated with an LOB. For each FB, one or more unplaced signals are selected for placement in the FB as a function of a number of unplaced output signals in the LOB with which the FB is associated (“current LOB”), a number of output pins in FBs associated with LOBs other than the current LOB, and a number of output pins in all FBs that are associated with the current LOB and that have no assigned output signals.

Abstract: Programmable devices and methods of programming programmable devices are described. In one embodiment, a complex programmable logic device (CPLD) is programmed by a remote host programming unit that provides the configuration data over a data communications link into a first data-holding location on the device all at one time. The device is then locally programmed under the influence of a controller that causes the configuration data in the first data-holding location to be written or copied to a second data-holding location on the device. In one embodiment, the first data-holding location is a rapidly programmed temporary memory (e.g., RAM), while the second data-holding location is a non-volatile memory that takes much longer to program (e.g., EEPROM or flash memory) and actually controls the device functionality. This technique frees up the host programming unit and the data communications link to attend to other matters, such as providing configuration data to other programmable devices.

Abstract: A method is provided for generating a pseudo-random sequence of integers, and the method is applied to the encryption of messages. The method uses a key K and a pair of prime numbers p and q, where q=2p+1. According to one aspect of the invention, a sequence of integers is formed. A sequence of bits is then formed from the sequence of integers, e.g., by selecting the least significant bit from each integer value. The sequence of bits is then used to encrypt a message using a selected encryption algorithm such as the XOR algorithm. Since prime numbers p and q can be selected to be larger than key K, the repeating period of the sequence of integers is larger than that permitted by the bit length of K.

Abstract: A method for analytical placement of cells using density surface representations. The placement of the cells is characterized as density surface fun which is two-dimensional and continuous. The cells are iteratively moved from areas having higher densities of placed cells to areas having lower densities of placed cells using the density surface function.

Abstract: An apparatus for implementing fast sum-of-products logic in an FPGA is disclosed. The apparatus includes a CLB including a plurality of slices and a second-level logic circuit to combine the outputs of the slices. Typically, the second-level logic circuit is an OR gate or its equivalent that implements the sum portion of the sum-of-products expression. Alternatively, a combining gate may be included within the slice to combine the output of one slice with the output of another slice. In this case the combing gates of each of the slices are connected in series to sum the result of the product operation of a given slice with the product operations from preceding slices. The slice may also include a dedicated function generator to increase the performance of each slice to implement wide functions, particularly sum-of-products functions. The dedicated function generator may include an AND gate and an OR gate with a multiplexer as a selector.

Abstract: A method is provided for remapping logic modules to resources of a programmable gate array. Connections are specified between at least two logic modules, wherein each module has a respective floorplan that includes a set of circuit elements. A first set of resources of the programmable gate array is compared to a second set of resources, wherein the second set of resources are those resources required by the sets of circuit elements. If the first set of resources covers the second set of resources, the floorplans of the logic modules are combined into a single floorplan that maps to the first set of resources.

Abstract: An input signal latching circuit for suppressing the effect of any ringing or other irregularities that occur within a specified time period after a transitional voltage level is reached, without significantly delaying the propagation of the input signal.

Abstract: A comparator circuit for detecting full and empty conditions in a first-in first-out (FIFO) memory system. The comparator circuit includes two-input logic circuits for comparing selected read and write addresses. An almost-empty condition is detected by comparing a next-to-be-used read address value with a currently-used write address value. When these address values are equal, high logic signals are passed by a set of mode control multiplexers to the select terminals of a series of carry chain multiplexers, thereby causing a high logic value to be transmitted to a data input terminal of a first register. The first register latches the high logic signal at the next rising edge of the read clock signal, thereby generating a high EMPTY control signal immediately after a final data value is read from the memory.

Abstract: A system and method for operating an asynchronous first in, first out (FIFO) memory system in which the amount of data stored in a FIFO memory is determined by re-synchronizing a binary read address from a read clock signal to a write clock signal, then subtracting the write-synchronized read address from the binary write address. The FIFO memory system includes the FIFO memory, read and write address counters for generating the binary read address and binary write address, respectively, and a write synchronization circuit. The binary read address is converted into a Gray-code value which is then synchronized to the write clock signal. The write-synchronized Gray-code read address value is then re-converted to binary to form the write-synchronized read address.

Abstract: A glitchless delay line using a Gray code multiplexer is provided. The glitchless delay line combines a multi-tap delay circuit with the Gray code multiplexer. Specifically, the multi-tap delay circuit provides a plurality-of sequentially ordered delayed output signals on a plurality of sequentially ordered output terminals. The Gray code multiplexer has a plurality of input terminals coupled to the sequentially ordered delayed output terminals. The Gray code multiplexer is controlled by driving a Gray code value onto the control terminals of the Gray code multiplexer to select a specific delayed output terminal of the multi-tap delay circuit. The delay provided by the delay line is increased by incrementing the Gray code value on the control terminals of the Gray code multiplexer and decreased by decrementing the Gray code value on the control terminals. Race conditions on the control lines are eliminated when incrementing or decrementing the Gray code value by one.

Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

Abstract: The programmable interconnect points (PIPS) associated with each tile of an FPGA are programmed in response to configuration data values stored in an array of configuration memory cells. Configuration memory cells that control the configuration of the interconnect structure of the tile are located in a rectangular block within the array. For example, the configuration memory cells that control the configuration of the interconnect structure may be located in several rows of the array. This configuration enables the interconnect structure of the tile to be easily modified. To add more interconnect lines to the FPGA, the additional interconnect lines and their associated PIPs are added to the interconnect structure, and the configuration memory cells required to program the PIPs are added as additional rows in the configuration memory cell array. The pattern of configuration memory cells remains unchanged, except for the added rows of configuration memory cells.

Abstract: Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit using resistive elements for which resistance varies with misalignment in one dimension. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between two conductive layers. Other embodiments measure misalignment between diffusion regions and conductors and between diffusion regions and windows through which other diffusion regions are to be formed. A circuit in accordance with one embodiment includes row and column decoders for independently selecting mask-alignment detection structures to reduce the number of test terminals required to implement the detection structures.

Abstract: Described are systems for producing differential logic signals and circuits for biasing the voltages of the differential logic signals. These systems can be adapted for use with different loads by programming one or more programmable elements. One embodiment includes a series of driver stages, the outputs of which are connected to one another. The driver stages turn on successively to provide increasingly powerful differential amplification. This progressive increase in amplification produces a corresponding progressive decrease in output resistance, which reduces the noise associated with signal reflection. The systems can be incorporated into programmable IOBs to enable PLDs to provide differential output signals.

Abstract: The Internet is used to test an integrated circuit chip that is provided with boundary scan circuitry and plugged into a circuit board at a customer's location. A host computer at the manufacturer's location runs a web page server having the ability to remotely test a customer's chip. The process is initiated by the customer connecting the circuit board to his own computer and logging onto the web site. The customer transmits customer identification and other data to the web server, which then transmits a downloader program and a JAVA program script to the customer's computer. The customer's computer then uses the downloader program to transmit high and low level device data describing the functionality of the chip to the host computer, which then generates and transmits a set of suitable test vectors to the customer's computer.

Abstract: With emergence of Bluetooth™ and other wireless standards, it has become increasingly desirable and practical to use low-cost wireless links, instead of cables, between devices, such as computers, printers, and personal digital assistants. Vital to these wireless links are the amplifiers that receive transmitted signals. One amplifier form, known as a common-gate amplifier, generally includes bias circuitry that requires large areas of an integrated-circuit chip or increases power usage and adds noise. Accordingly, the inventor devised an exemplary common-gate amplifier that includes an inductor coupled between the gate and drain of an amplifying transistor. The inductor acts as a short circuit at low frequencies, forcing the transistor to function at these frequencies as a diode and thus reduces the need for further bias circuitry. Other inventive embodiments include wireless receivers, transceivers, programmable integrated circuits, and electronic devices that incorporate the exemplary amplifier.

Abstract: One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one embodiment, a multi-function tile includes a configurable, dual-ported RAM and a multiplier that share routing resources of the multi-function tile. The RAM includes first and second input ports coupled to first and second input data buses, respectively, and includes first and second output ports coupled to first and second output data buses, respectively. The multiplier includes first and second operand ports coupled to receive operands from the first and second input data buses, and in response thereto provides a product. In one embodiment, the most significant bits (MSBs) of the product are selectively provided to the first output data bus using bus multiplexer logic, and the least significant bits (LSBs) of the product are selectively provided to the second output data bus using bus multiplexer logic.

Abstract: A logic element for a programmable logic device (PLD) can be configured as a shift register of variable length. An array of memory cells in the logic element is divided into two or more portions. The memory cells of each portion supply values to a corresponding output multiplexing circuit, thereby enabling the logic element to function as a lookup table by combining the outputs of the multiplexing circuits. However, each portion is also configurable as a shift register. The portions can function as separate shift registers, or can be concatenated to function as a single shift register. In some embodiments, the portions can also be concatenated with shift registers in other logic elements. Because two or more output multiplexing circuits are available, two or more taps are provided, one from each portion of the memory array.

Abstract: A circuit and method are provided for stress-testing EEPROMS by incrementally selecting and deselecting word lines. The circuit of the invention comprises a memory cell array, a set of decoders for decoding a memory address bus and controlling word lines for the memory cell array, a control circuit, and a shift register driven by the control circuit. Each bit of the shift register has the capability of overriding a group of one or more of the decoders. When the initiation signal is received by the control circuit, a state control bit is set high and is clocked through the shift register. The high bit overrides successive groups of decoders as it is shifted through the shift register, until all word lines in the memory cell array are selected. After the stress test has been performed, the state control bit is returned to zero and is cycled through the shift register on successive clock cycles, incrementally deselecting groups of word lines until all word lines are deselected.

Abstract: A first in, first out (FIFO) memory system and method in which the full or empty condition of the FIFO memory is detected before the FIFO memory is actually full or empty, thereby allowing the generation of FULL or EMPTY control signals immediately after a last data value is written into or from the FIFO memory. An almost-empty condition, is detected by comparing the read address and write address values. When the read and write address values indicate that one data value remains in the FIFO memory and a read operation is about to be performed, an ALMOST_EMPTY control signal is applied to a data input terminal of a first register that is clocked by a read clock signal. The ALMOST_EMPTY control signal is latched by the first register at the next rising edge of a read clock signal, thereby causing the register to generate a high EMPTY control signal in the same read clock cycle during which the last data value is read from the FIFO memory.