Abstract: A delay lock loop uses a clock phase shifter with a delay line to synchronize a reference clock signal with a skewed clock signal. The delay line is coupled to a reference input terminal of the delay lock loop and generates a delayed clock signal that is provided to the clock phase shifter. The clock phase shifter generates one or more phase-shifted clock signals from the delayed clock signal. An output generator coupled to the delay line, the clock phase shifter, and an output terminal of the delay lock loop provides either the delayed clock signal or one of the phase-shifted clock signals as an output clock signal of the delayed lock loop. The propagation delay of the delay line is set to synchronize the reference clock signal with the skewed clock signal, which is received on a feedback input terminal of the delay lock loop.

Abstract: Described is a method of using place-holding cells, or “stopper cells,” to force a place-and-route tool to route a selected signal path through a particular physical location on a semiconductor die. In one method, phantom blocks, created from the design specification, define the area, logic, timing, and the placement of input/output (I/O) ports for a number of custom blocks. These phantom blocks are combined with any standard blocks to create a high-level description of a desired circuit. Then, for each I/O port of the custom blocks, a place-holding cell, or “stopper cell,” is added to the description in the path defined between the I/O port and its source or destination. The stopper cells are then grouped with the associated custom blocks and the resulting collection of stopper cells and blocks are placed and routed. Completed custom blocks can then be substituted for respective phantom blocks after place and route. Stopper cells preserve complex routing during this substitution.

Abstract: A method is disclosed for reconfiguring an on-board FPGA of an interface device without resetting the interface device. The FPGA interface device also includes a microcontroller, and the on-board FPGA has a serial data port coupled to a first, non-volatile memory and a parallel data port coupled to a second memory, which may be a volatile memory. The default configuration design is stored in the non-volatile memory. The on-board FPGA is initially in a serial configuration mode such that upon power-up, the on-board FPGA looks to the first memory via its serial port for the configuration design. Where it is desired to reconfigure the on-board FPGA, a new configuration design is stored in the second memory, and the on-board FPGA is instructed to reconfigure itself in parallel mode. In response thereto, the on-board FPGA looks to the second memory via its parallel port, retrieves the new configuration design, and then reconfigures itself accordingly.

Abstract: A ramping circuit gradually applies an erasing voltage to a memory cell. Within the ramping circuit an NMOS transistor is disclosed which gradually supplies the erasing voltage to the memory cell in response to an external ramping voltage. The NMOS transistor supplies the erasing voltage until the loss voltage of the transistor limits a maximum erasing voltage that the NMOS transistor can supply. The specification then discloses a PMOS transistor which operates to supply the erasing voltage to the memory cell when the NMOS transistor can no longer do so. The PMOS transistor is connected to control circuitry which keeps the PMOS transistor inactive until the output voltage of the NMOS transistor is limited by its voltage loss.

Abstract: Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit using resistive elements for which resistance varies with misalignment in one dimension. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between two conductive layers. Other embodiments measure misalignment between diffusion regions and conductors and between diffusion regions and windows through which other diffusion regions are to be formed. A circuit in accordance with one embodiment includes row and column decoders for independently selecting mask-alignment detection structures to reduce the number of test terminals required to implement the detection structures.

Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

Abstract: A method is provided for securely configuring an FPGA with macros. Specifically, if an end user desires to use a macro from a macro vendor, the end user creates a design file containing an encrypted macro received from the macro vendor rather than the actual macro. The end user uses a FPGA programming tool to convert the design file into configuration data. Specifically, the FPGA programming tool processes the design file to detect encrypted macros. If an encrypted macro is detected, the FPGA programming tool requests authorization over a secured medium to decrypt the encrypted macro from the macro vendor. If authorization is received, the FPGA programming tool decrypts the encrypted macro and converts the design file into configuration data incorporating the macro.

Abstract: A field programmable gate array configured to use RAM control signals as routing and/or logic resources. By using RAM bit lines as routing, and/or to implement Wire-OR functions, and/or with word lines to implement PAL functions, one may increase the efficiency of lines normally used only for programming the control memory.

Abstract: A method is provided for securely configuring an FPGA with macros. Specifically, if an end user desires to use a macro from a macro vendor, the end user creates a marked design file containing a macro marker rather than the actual macro. The marked design file is converted into configuration data by a macro manager. Specifically, the macro manager obtains the macro from the macro vendor and replaces the macro marker with the macro prior to converting the design file into configuration data. The macro manager provides the configuration data to the end user. Because only the macro manager has access to the macro, the possibility of unlicensed use of the macro is diminished.

Abstract: In a charge pump system, the frequency of an oscillator is based on the output signals from a plurality of differential amplifiers. Each differential amplifier receives a different reference voltage as well as a common input voltage derived from the pumped voltage. A predetermined logic signal output by the differential amplifiers modifies, i.e. reduces, an original frequency of the oscillator. In this manner, the charge pump system quickly compensates for any overshoot in the pumped voltage in a manner directly correlated to the magnitude of the pumped voltage. If no differential amplifiers output the predetermined logic signal, then the oscillator generates the original frequency. In this manner, the charge pump system also compensates for any undershoot in the pumped voltage by providing the fastest frequency.

Abstract: A configurable logic block (CLB) having a plurality of identical configurable logic element (CLE) slices is provided. Each CLE slice includes a plurality of function generators (lookup tables) that can be configured to form a random access memory (RAM). The width and depth of the RAM are selectable by controlling the routing of signals within the CLE slices. A hierarchy of wide function multiplexers (F5, F6, and F7 multiplexers) are provided to selectively route read data values from the lookup tables. Another set of multiplexers is used to selectively route write data values to the lookup tables. These multiplexers can be configured to provide a single write data value to all of the lookup tables to form a deep RAM. Alternatively, these multiplexers can be configured to provide one write data value to half of the lookup tables, and another write data value to the other half of the lookup tables.

Abstract: The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.

Abstract: The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters that may, for example, include the required timing, data width, number of taps for a FIR filter, and so forth. SIMs are called “self implementing” because they encapsulate much of their own implementation information, including mapping, placement, and (optionally) routing information. Therefore, implementing a SIM-based design is significantly faster than with traditional modules, since much of the implementation is already complete and incorporated in the SIM.

Abstract: Described are programmable routing resources capable of distributing low-skew signals along more than one edge of a programmable logic device (PLD). The PLD includes groups of input/output blocks (IOBs) arranged along each edge. A programmable signal-distribution tree can be configured to send a shared, low-skew signal to IOBs along adjacent edges. These signals are conveyed via perpendicular conductive lines that run parallel to the respective edges. Each conductive line can be programmably connected to a source of the shared signal using a respective programmable-interconnect point located near the corner of the PLD defined by the two edges.

Abstract: The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.

Abstract: A semiconductor device tester and handler interface includes tester and handler boards with a coplanarity plate between them. The handler board includes a central area adapted to mount semiconductor devices to be tested by a tester. The tester board has tester contacts located to interface with a tester. During cold testing, to avoid condensation on the side of the handler board away from the devices being tested, dry gas is applied to the region formed by the coplanarity plate. During hot testing, flowing dry gas prevents the hot handler board from excessively heating the tester board and associated tester.

Abstract: An apparatus and method for testing “chip scale” integrated circuits (IC's) using a vertical probe card mounted on a printed circuit board (PCB). A nesting assembly mounted over the vertical probe card includes alignment walls and an alignment plate including chamfered through holes. The alignment walls are slanted to provide rough alignment of the IC within the nesting assembly, and fine alignment of the IC is achieved when the solder balls extending from the IC are received in the chamfers formed in the upper surface of the alignment plate. Tips of formed wire probes extend from the vertical probe card towards the bottom surface of the alignment plate. When the alignment plate is pushed towards the vertical probe card by a device handler, the tips of the wire probes extend through the through-holes and pierce the solder balls of the IC, providing electrical contact between the IC and the PCB.

Abstract: A programmable logic device (PLD) includes at least one function generator capable of implementing any arbitrarily defined Boolean function of input signals. The PLD includes a dynamically controlled multiplexer (MUX) on each function-generator input terminal. The inputs of each MUX can be routed to the corresponding function-generator input terminal by providing an appropriate select signal on one or more control lines. One embodiment of the PLD includes a programmable look-up table (LUT) that permits routing software to determine the correspondence between the MUX input terminals and a user-defined selection code on the MUX select lines. In one embodiment, the correspondence between the NUX input terminals and the selection code is established by configuring a number of programmable memory cells in the LUT. Another embodiment enhances programming flexibility with an additional MUX connected between the control lines and the LUT.

Abstract: An field programmable gate array (FPGA) of cells arranged in rows and columns is interconnected by a hierarchical routing structure. Switches separate the cells into blocks and into blocks of blocks with routing lines interconnecting the switches to form the hierarchy. Also, select units for allowing memory bits to be addressed both individually and in large and arbitrary groups are disclosed. Further a control store for configuring the FPGA is addressed as an SRAM and can be dynamically reconfigured during operation.

Abstract: A memory array having a read mode and a write mode is addressed using separate read and write decoders. The write decoder is used to write bit values to one column of the array. A hard-wired read decoder is utilized to further increase the operating speed during the memory read mode. In one embodiment, a separate read bit line is provided to facilitate faster read operations. In an exemplary embodiment, the write decoder receives two input signals and generates four write address signals on write word lines that are transmitted to the columns of programmable elements of a logic/memory array. The hard-wired read decoder also receives the same two input signals, and generates eight read address signals on two read word lines, two read address signals being transmitted to each column of the logic/memory array.