Abstract: Two-dimensional discrete wavelet transform analysis and synthesis banks. In various embodiments, a cascade combination of two one-dimensional wavelet transforms is implemented, along with a set of memory buffers between the two stages. The memory buffers store intermediate results between the stages of the two-dimensional discrete wavelet transform, thereby eliminating off-chip memory references.

Abstract: The present invention provides a new method to handle power and ground signals in modular design of programmable logic devices. During module implementation, the power and ground signals of each module are associated with area constraint properties. When performing routing in the module implementation phase, the power and ground signals together with regular local signals of the module are routed in accordance with their respective area constraint properties. However, the area constraint properties of the power and ground signals are removed during assembly phase while the area constraint properties of the local signals are retained.

Abstract: Output circuits that provide compatibility with various input and output voltage levels without sacrificing performance. A pull-up on an output terminal is gated by an internal node, and the invention encompasses various circuits and means for placing a data input signal on this internal node. One embodiment includes a level shifter on the data input path, while also providing an alternative path through the output circuit that bypasses the level shifter. When the input data value goes high, the alternative path quickly places an attenuated high value on the internal node. The level shifter then becomes active and raises the voltage on the internal node to the output power high level, ensuring that the output pull-up is completely off.

Abstract: An FPGA has an on-chip processor that reads configuration data onto the FPGA and controls the loading of that configuration data into FPGA configuration memory cells. After FPGA power-up, the processor reads a configuration mode code from predetermined terminals of the FPGA. If the configuration mode code has a first value, then the processor executes a first configuration program so that configuration data is received onto the FPGA in accordance with a first configuration mode. If the configuration mode code has a second value, then the processor executes a second configuration program so that configuration data is received onto the FPGA in accordance with a second configuration mode. The configuration programs can be stored in metal-mask ROM on-chip so they can be changed without re-laying out the remainder of the FPGA. Providing multiple configuration programs allows the FPGA to support multiple configuration modes using the same processor hardware.

Abstract: A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal silicide layers stacked over a similarly shaped gate oxide. The gate heating structure includes a fusible portion in the metal silicide layer formed over the channel region. In an unprogrammed state, the memory cell operates as a conventional MOS transistor, with current flow between the source and drain regions being controlled by a control voltage applied to the metal silicide layer. However, when a programming voltage is applied across the metal silicide, layer, the fusible portion agglomerates, generating intense localized heating. In an embodiment of the invention, the memory cell is an NMOS device. Tie heating causes segregation of the channel dopant atoms towards the source and drain regions, lowering the threshold voltage of the device.

Abstract: A clock divider circuit includes a state machine that receives an input clock signal and generates mutually exclusive set and reset control signals. The set and reset control signals are used to control set and reset passgates, respectively, selectively providing the input clock signal to the gate terminals of a pullup and a pulldown on the output node. The set and reset control signals are also provided to a keeper circuit that maintains a value placed on the output node.

Abstract: The present invention provides an improved semiconductor flipchip package that includes a central cavity area on the first major side for receiving a flipchip die therein. The package substrate is substantially made from a single material that serves as the support and stiffener and provides within the cavity floor all the connecting points for flipchip interconnection to the silicon die. The integral cavity wall serves as a stiffener member of the package and provides the required mechanical stability of the whole arrangement without the need for a separate stiffener material to be adhesively attached. The cavity walls may contain extra routing metallization to create bypass capacitors to enhance electrical performance. The invention discloses optional methods to cover the silicon die to enhance thermal performance of the package.

Abstract: An anti-aliasing filter with adaptable cutoff frequency. In various embodiments, the filter includes a calibrator/adaptor section and an anti-aliasing filter section. Both sections include a cascaded arrangement of adjustable delay circuits, and the calibrator/adaptor section includes a control circuit. A reference signal is input to the delay circuits and the control circuit of the calibrator/adaptor section, and an analog input signal is input to the delay circuits of the anti-aliasing filter. The control circuit compares the directly received reference signal to the reference signal from the last delay circuit and generate an adjustment signal responsive to the comparison. The delay intervals of all the delay circuits are adjustable responsive to the adjustment signal from the control circuit.

Abstract: An FPGA architecture and method to reduce the size of the bitstream used in configuring or reconfiguring the FPGA. To facilitate features of the compression process, an FPGA is modified to implement an addressable data register in place of a conventional shift register. This allows data frames to be arranged in order of similarity, and a bitstream formed from one full data frame along with an address into which the frame is to be loaded, and subsequent partial data frames including only changed words along with the row address of the changes and the column address into which modified frames are to be loaded, rather than shifting in entire frames of data for subsequent frames.

Abstract: A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations.

Abstract: A segmented digital-to-analog converter (DAC) has been described that uses a two-step calibration process to calibrate current sources to a single primary reference source. In one embodiment, the DAC includes sub-DACs, a reference generator circuit and a primary, or golden, reference source. Current sources of both the sub-DACs and the reference generator are calibrated to a golden current source or primary reference current. In one embodiment, the current sources each include a transistor coupled so that a gate voltage can be adjusted during calibration. The multiple current sources of the reference generator are first calibrated to the primary reference source. The calibrated output currents of the reference generator are then used to calibrate current sources in the sub-DACs.

Abstract: Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. Similarly, reduced input/output blocks and reduced matrices are derived from the configuration data for input/output blocks and programmable switch matrices of the FPGA, respectively. The reduced logic blocks are arranged in a similar layout to the original CLBs so that timing relationships remain similar in the RFPGA and FPGA. The actual timing of the RFPGA can be modified by increasing or decreasing the timing delay on various signal paths based on the FPGA design or additional timing constraints.

Abstract: An improved CLB architecture, wherein the use of dedicated AND gates to generate a carry chain input signal facilitates low latency multiplication and makes efficient use of four-input function generators. In one embodiment of the invention, when multiplication using a binary addition tree algorithm is used, AND gates to implement single-bit multiplication are provided within the available function generators and duplicated in a dedicated AND gate accessible outside the corresponding function generator as a carry-chain input signal. In another embodiment, carry chain multiplexers can be selectively configured as AND or OR gates to facilitate certain arithmetic or comparison functions for the outputs of a plurality of function generators.

Abstract: Method and apparatus for routing input signals having different voltage requirements in a PLD circuit design. In various example embodiments, the input signals are grouped into logical clusters, wherein the input signals in each logical cluster have a common input voltage standard. Input pins of the device are grouped into physical clusters, wherein each physical cluster is associated with a voltage standard. Each of the physical clusters is paired with a logical cluster and has associated therewith one or more programmable logic elements as determined by the input signals to be routed to the programmable logic elements. For each paired logical cluster and physical cluster, the input signals of the logical cluster are routed from the pins of the physical cluster to the programmable logic elements of the physical cluster.

Abstract: A programmable logic device (PLD) implementing an SDRAM controller is provided. The configurable logic of the PLD forms an interface between the system and the SDRAM, as well as a state machine to operate the controller and the interface. In this manner, many functions of the SDRAM controller can be selectively controlled and easily changed by reprogramming the PLD. The configurable logic of the PLD also forms a state machine to operate the controller and the interface. In accordance with the present invention, dedicated circuits of the PLD optimize performance of the SDRAM controller. These dedicated circuits include two delay locked loops (DLLs) which eliminate skew between the system clock, a global clock in the PLD, and the SDRAM clock.

Abstract: A system and method for configuring routing resources of a programmable logic device are presented in various embodiments. In one embodiment, a first function is provided that automatically generates configuration bits for configuration of routing resources to connect a source to a sink. The input parameters to the to the first function include the source and the sink. A second function is provided to automatically generate configuration bits for configuration of routing resources that connect a source to a plurality of sinks. The second function is responsive to input parameters specifying the source and plurality of sinks. Additional program interfaces are provided and each provides various controls over the routing process.

Abstract: Methods for designating target locations for circuit elements to be implemented in a programmable system. A target system is divided into blocks at various levels of hierarchy, with each block within the same higher-level block having a different identifier. A user can specify a desired location for a circuit element at any or all of these levels of hierarchy. Preferably, a desired location is specified using a single location constraint comprising a string of identifiers separated by delimiters. In one embodiment, a uniform coordinate system is applied to all blocks at a given level, even in a non-uniform programmable array. In this embodiment, a non-uniform array of logic blocks is divided into tiles, and a uniform coordinate system is applied to the tiles. Thus, any tile in the array can be addressed using a uniform coordinate system, regardless of the nature of the logic blocks comprising the tile.

Abstract: A method is disclosed for communicating with an FPGA interface device having a microcontroller when the on-board microcontroller is not responsive to commands from a host system. If the host system determines that the microcontroller is not responsive to commands, the host system sends a null character to the interface device at a predetermined baud rate which is significantly distinguishable from baud rates normally used for communicating with the microcontroller. A logic circuit on the interface device monitors the baud rate of incoming data, and if a null character at the predetermined baud rate is detected, the logic circuit toggles the reset pin of the microcontroller. In response thereto, the microcontroller re-boots itself, and is thereafter able to communicate with the host system. Additional commands are provided to the interface device by using other baud rates which are significantly distinguishable from the baud rates normally used.

Abstract: A method and apparatus for implementing incremental design changes. In various embodiments, primary outputs of a new design are compared for logical equivalence to corresponding primary outputs of a prior implementation. If the logic is equivalent, the implementation of the primary outputs from the prior implementation is reused to implement the corresponding primary outputs of the new design.

Abstract: A method and apparatus for automatic, timing-driven implementation of a circuit design. In one embodiment, the different phases of implementing a circuit design are iteratively performed using timing constraints that are automatically and dynamically generated in each iteration. The process aids in identifying and achieving a maximum performance level of the implemented design. In another embodiment, selected numbers of critical connections are used to dynamically vary the timing constraint. In general, a number of connections is automatically selected from the circuit design and used to derive a new timing constraint to be applied in the next iteration. Slack values associated with paths in the design are also used in deriving the new timing constraint.