Abstract: An adapter cable can include a receptacle connector including contact pins as defined for a peripheral component interconnect express (PCIe) connector; edge connectors having edge pins as defined for a PCIe add-in card (AIC); and connections connecting the receptacle connector to the edge connectors, each connection connecting one of the contact pins to one of the edge pins.

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a stack structure including interleaved conductive layers and dielectric layers, a doped semiconductor layer, and a channel structure extending through the stack structure and in contact with the doped semiconductor layer. The channel structure includes a composite dielectric film and a semiconductor channel along a first direction. The composite dielectric film includes a gate dielectric portion and a memory portion along a second direction perpendicular to the first direction. A part of the gate dielectric portion faces, along the first direction, one of the conductive layers that is closest to the doped semiconductor layer.

Abstract: A method of operating the memory system includes determining a boundary page line to be found, the boundary page line including a first page line of page lines in a programming order. States of pages forming the first page line of the page lines in the programming order are all erased state. The method also includes obtaining an address of a frozen page line, the frozen page line including a first page line of a first page line group. States of at least part of pages forming the first page line of the first page line group are erased state. The method further includes determining that states of pages forming the frozen page line are all programmed state. The method further includes determining the page line group to which the boundary page line belongs according to the address of the frozen page line. The method further includes determining an address of the boundary page line from the page line group to which the boundary page line belongs.

Abstract: An operating method for a memory, a memory, and a memory system are provided in the present application. The memory includes at least a plurality of word lines and a plurality of strings, and the plurality of word lines include a target word line, and each word line is coupled to a plurality of strings. Each string includes a plurality of memory cells. In accordance with the operating method provided by the present application, the first verification and the second verification are performed on a plurality of target memory cells with first and second verify voltages during performing a first programming operation on a plurality of target memory cells in target string coupled to the target word line, and the second start program voltage is determined based on at least the second verification result, ensuring the accuracy of the second start program voltage.

Abstract: A method includes applying a first read voltage to a word line corresponding to a first word line address in a first read request instruction. The method also includes detecting an obtained second read request instruction. The method further includes when the second word line address included in the second read request instruction is the same as the first word line address, applying a second read voltage to the word line corresponding to the first word line address after the end of the application of the first read voltage.

Abstract: A method of operating a memory system can include maintaining one or more last write page table, the one or more last write page table is periodically updated to include at least one page serial number of the last page being written in a flash media, determining a last checkpoint in the flash media, the checkpoint is periodically updated and saved, determining the at least one page serial number in the one or more last write page table, validating a page having a highest page serial number in the one or more last write page table, validating pages having page serial numbers after the validated page having a page serial number in the one or more last write page table until an uncorrectable error correction code (UECC) occurs, and rebuilding mapping tables according to pages from the last checkpoint up to the last validated page before the UECC occurs.

Abstract: A method of programming a memory device. The memory device includes a plurality of memory strings, each memory string including a top transistor controlled by a top select gate (TSG) and connected to a bit line (BL), a bottom transistor controlled by a bottom select gate (BSG), and memory cells between the top and bottom transistors, each memory cell connected to a word line (WL). The method includes applying program pulses to a memory cell of the memory device in a program phase, verifying a voltage value of the memory cell in a verify phase, receiving a suspend command and performing a suspend operation, applying a discharge pulse to the memory cell in a discharge phase to thereby discharge the memory cell, wherein the discharge pulse includes a voltage pulse to an unselected top select gate (TSGunsel), and suspending programming or verifying of the memory cell in a suspend phase.

Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes disposing an alternating dielectric stack over a substrate, wherein the alternating dielectric stack includes first dielectric layers and second dielectric layers alternatingly stacked on the substrate. The method also includes forming a channel structure penetrating through the alternating dielectric stack and extending into the substrate, wherein the channel structure includes a channel layer disposed on a sidewall of a memory film. The method further includes removing the substrate and a portion of the memory film that extends into the substrate to expose a portion of the channel layer; and disposing an array common source (ACS) on the exposed portion of the channel layer.

Abstract: According to one aspect of the present disclosure, a memory system is provided. The memory system may include at least one non-volatile memory device and a memory controller coupled to the at least one non-volatile memory device. A multi-level mapping table may be stored in the memory device. The multi-level mapping table may be configured to implement mapping from a logical address to a physical address. The memory controller may include a buffer. A portion of the multi-level mapping table may be stored in the buffer. The memory controller may be configured to perform a random read operation on the data stored in the memory device. In response to a random read range corresponding to the random read operation meeting a preset condition, the memory controller may be configured to adjust capacity for storing different levels of mapping tables in the buffer.

Abstract: The present disclosure describes a three-dimensional (3D) memory device includes first and second memory arrays disposed on a semiconductor layer. The 3D memory device can also include a staircase structure disposed between the first and second memory arrays. The staircase structure includes first and second staircase regions. The first staircase region includes a first staircase structure that contains a first plurality of stairs descending in a first direction. The second staircase region includes a second staircase structure that contains a second plurality of stairs descending in a second direction. The 3D memory device can also include a contact region disposed between the first and second staircase regions. The contact region includes a plurality of contacts the extending through an insulating layer and into the semiconductor layer.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, a semiconductor layer, a supporting structure, a spacer structure, and a contact structure. The memory stack includes interleaved conductive layers and dielectric layers and includes a staircase region in a plan view. The semiconductor layer is in contact with the memory stack. The supporting structure overlaps the staircase region of the memory stack and is coplanar with the semiconductor layer. The supporting structure includes a material other than a material of the semiconductor layer. The spacer structure is outside the memory stack and is coplanar with the supporting structure and the semiconductor layer. The contact structure extends vertically and is surrounded by the spacer structure.

Abstract: Implementations of the present disclosure disclose a memory system and an operation method thereof. The memory system comprises at least one memory device and a memory controller coupled with the at least one memory device. The memory controller is configured to: in respond to an instruction of a host coupled with the memory system, control the memory system to enter a first activation mode and a transition mode sequentially. The transition mode includes an idle mode and a first sleep mode. A power of the memory system in the first sleep mode is less than a power of the memory system in the idle mode. The power of the memory system in the idle mode is less than a power of the memory system in the first activation mode.

Abstract: In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A first semiconductor structure including an array of NAND memory strings is formed on a first substrate. A second semiconductor structure including a recess gate transistor is formed on a second substrate. The recess gate transistor includes a recess gate structure protruding into the second substrate. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the array of NAND memory strings is coupled to the recess gate transistor across a bonding interface.

Abstract: Implementations of the present disclosure provide a memory system, an operation method thereof, and a computer-readable storage medium. The memory system includes at least one non-volatile storage device and a controller coupled to the non-volatile storage device, where each of the non-volatile storage devices includes a plurality of blocks, and at least one block in at least one of the non-volatile storage devices constitutes a super block. The controller may be configured to determine sorting of a plurality of super blocks based on an erase count of each super block and a number of bad blocks in each super block. The erase counts of any two adjacent super blocks in the sorting may meet a preset requirement, first super blocks in the sorting may be arranged at intervals, and a number of bad blocks in the first super block may be greater than a preset value.

Abstract: A circuit includes a voltage generator and a sensing device. The voltage generator includes a first output and a second output. The first output is configured to output a word line voltage, and the second output is configured to output a flag signal indicates a relationship between the word line voltage and a reference signal. The sensing device includes a first input and a third output. The first input is coupled to the second output of the voltage generator, and the third output of the sensing device is configured to output a value corresponding to capacitance change of word line capacitance loading based on the flag signal.

Abstract: A method for operating a memory system relates to the memory field and aims to address problems such as the over-long waiting time caused by moving data during the buffer flush process. The method for operating the memory system includes: in response to a first space flush command, configuring a part of the free space as the available space of the first space in the case where the size of the free space of the memory device is greater than or equal to the first threshold.

Abstract: A page buffer circuit of a memory device includes a first sensing branch including a first pre-charge path and a low-voltage latch, and a second sensing branch including a second pre-charge path and a sensing latch. The first sensing branch and the second sensing branch are parallel coupled to a sensing node of the page buffer circuit.

Abstract: A method of operating a non-volatile memory including an unselected word line is provided. A first voltage rising at a first slope is applied by a voltage generator to the unselected word line. Outputting the first voltage is stopped by the voltage generator in response to that the first voltage rises to a predetermined voltage, wherein the predetermined voltage is higher than a pass voltage. The pass voltage is outputted by the voltage generator to the unselected word line.

Abstract: Implementations of the present disclosure disclose a memory controller and a control method thereof, a memory apparatus and a control method thereof, and a memory system and a control method thereof.

Abstract: Aspects of the disclosure provide the memory system having a memory apparatus and a memory controller coupled with the memory apparatus. The memory apparatus includes at least one memory chip having a plurality of memory planes, each memory plane includes a plurality of pages, a plurality of pages located at the same position in each of the memory planes of the at least one memory chip form a page line, the memory apparatus includes a plurality of tag groups, each tag group includes a plurality of page lines. The memory controller can be configured to, when the memory apparatus is powered down and then powered on, respectively perform, in sequence, a recoding operation on all pages of which the states are programmed states in each tag group, and according to an encoding result corresponding to each tag group, respectively determine whether check data corresponding to each tag group is abnormal.