Abstract: In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A transistor is formed in a first region on a first side of a single crystalline silicon substrate. A step layer is formed in a second region on the first side of the single crystalline silicon substrate. A channel structure extending through a stack structure and in contact with the step layer is formed. The stack structure includes interleaved dielectric layers and conductive layers on the step layer. Part of the single crystalline silicon substrate that is in the second region is removed from a second side opposite to the first side of the single crystalline silicon substrate to expose the step layer from the second side.

Abstract: A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).

Abstract: A method includes disposing a layer stack on a substrate, the layer stack including a number of levels. A first control gate structure is formed in a first level of the number of levels by: forming a first opening through a dielectric layer of the first level and a sacrificial layer of the first level; removing a remaining portion of the sacrificial layer of the first level to form a first cavity; and disposing a first conductive layer in the first cavity. A second control gate structure is formed in a second level below the first level by: extending the first opening into a dielectric layer of the second level and a sacrificial layer of the second level to form a second opening; removing a remaining portion of the sacrificial layer of the second level to form a second cavity; and disposing a second conductive layer in the second cavity.

Abstract: In certain aspects, a memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor coupled to the array of memory cells through at least one of the plurality of bit lines. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode.

Abstract: In certain aspects, a memory device includes a vertical transistor including a semiconductor body extending in a first direction, a stack structure including interleaved dielectric layers and conductive layers each extending perpendicularly to the first direction, an electrode layer including a conductive material and coupled to a first end of the semiconductor body, and a storage layer over the electrode layer. The electrode layer and the storage layer extend in the first direction through the stack structure.

Abstract: A memory device includes selected word lines coupled to first memory cells, a first group of unselected word lines coupled to second memory cells, a second group of unselected word lines coupled to third memory cells; and a peripheral circuit coupled to the selected word lines, the first group of unselected word lines, and the second group of unselected word lines. The peripheral circuit is configured to apply program voltages on the selected word lines, apply first pass voltages on the first group of unselected word lines; and apply second pass voltages on the second group of unselected word lines. A first maximum value of the first pass voltages is different from a second maximum value of the second pass voltages.

Abstract: A method of erase verification of a memory includes performing a first erase verification operation on a memory block of the memory after performing an erase operation on the memory block. The method also includes determining a first verification result of the first erase verification operation. The method further includes determining whether to perform a second erase verification operation on the memory block based on the first verification result. The second erase verification operation is configured to determine whether there is inter-word line leakage in the memory block.

Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a dielectric stack on the bottom conductive layer, the dielectric stack comprising a plurality of alternatively arranged first dielectric layers and second dielectric layers; forming an opening penetrating the dielectric stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and replacing the plurality of second dielectric layers with conductive layers.

Abstract: A memory includes at least a target word line and a first word line group and a second word line group respectively stacked on both sides of the target word line. The first word line group includes first word lines, and the second word line group includes second word lines. A method for operating the memory includes, during a pre-charge operation, applying a first bias voltage signal to the plurality of first word lines, applying a second bias voltage signal to a target word line, and applying a third bias voltage signal to the plurality of second word lines. The method also includes, during a programming operation, applying a program voltage signal to a target word line.

Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes sequentially forming a first and a second dielectric stacks on a substrate. The first dielectric stack includes a first and a second dielectric layers alternatingly stacked in a first direction perpendicular to the substrate. The second dielectric stack comprises a third and a fourth dielectric layers stacked in the first direction. The method further includes forming an etch-stop layer on the second dielectric stack and forming a gate line slit (GLS) trench spacer to cover a sidewall of the etch-stop layer. The method further includes replacing the fourth and the second dielectric layers with conductive layers through a GLS opening to form a top select gate (TSG) film stack and a film stack of alternating conductive and dielectric layers, respectively.

Abstract: A 3D-NAND memory device is provided. The memory device includes a substrate, a bottom select gate (BSG) disposed over the substrate, a plurality of word lines positioned over the BSG with a staircase configuration and a plurality of insulating layers disposed between the substrate, the BSG, and the plurality of word lines. In the disclosed memory device, one or more first dielectric trenches are formed in the BSG and extend in a length direction of the substrate to separate the BSG into a plurality of sub-BSGs. In addition, one or more common source regions are formed over the substrate and extend in the length direction of the substrate. The one or more common source regions further extend through the BSG, the plurality of word lines and the plurality of insulating layers.

Abstract: The present disclosure provides a memory system with a non-volatile memory that includes a plurality of storage areas. Each storage may include a plurality of first storage groups in a first area and a plurality of second storage groups in a second area. The first area may support physical addressing. The second area may not support physical addressing. A memory controller of the memory system may perform a wear leveling process by swapping a first storage group having a first group write count with a second storage group having a second group write count. The first group write count may be a maximum group write count among a plurality of group write counts corresponding to the plurality of first storage groups. The second group write count may be a minimum group write count among a plurality of group write counts corresponding to the plurality of second storage groups.

Abstract: A three-dimensional (3D) memory device includes a first memory cell, a second memory cell, a control gate between the first and second memory cells, a top contact coupled to the first memory cell, and a bottom contact coupled to the second memory cell. The first memory cell can include a first pillar, a first insulating layer surrounding the first pillar, a first gate contact coupled to a first word line, and a second gate contact coupled to a first plate line. The second memory cell can include a second pillar, a second insulating layer surrounding the second pillar, a third gate contact coupled to a second word line, and a fourth gate contact coupled to a second plate line. The 3D memory device can utilize dynamic flash memory (DFM), increase storage density, provide multi-cell storage, provide a three-state logic, decrease leakage current, increase retention time, and decrease refresh rates.

Abstract: The present disclosure provides a three-dimensional NAND memory device, comprising a NAND string including a memory cell to be inhibited to program, a word line driver, and a controller configured to control the word line driver to perform a programming operation on the memory cell controlled by a selected word line of a plurality of word lines including a first unselected word line adjacent to the selected word line, a first plurality of unselected word lines adjacent to the first unselected word line, and a second plurality of unselected word lines adjacent to the first plurality of unselected word lines. The programming operation includes applying a programming voltage signal to the selected word line; applying a first pass voltage to the first plurality of unselected word lines; and applying a second pass voltage to the second plurality of unselected word lines, the first pass voltage is different from the second pass voltage.

Abstract: Aspects of the disclosure are directed to a memory system that can include a controller and a memory coupled thereto, each memory cell of the memory is configured to store m-bit information, and the controller includes at least one of an exclusive OR circuit, an inverter and an access circuit. The controller is configured to receive n groups of logic page data, and generate, at different values of m and n, at least one group of logic page data selectively by at least one of the exclusive OR circuit, the inverter and the access circuit. The controller is further configured to transmit the m groups of logic page data to the memory to generate 2n different data states in the memory.

Abstract: A method of configuring an on-die termination circuit in each non-volatile memory die of a plurality of non-volatile memory dice that have one or more pads coupled in common, includes determining, by each of the non-volatile memory dice whether that non-volatile memory die is a target or a non-target for a memory operation; setting, by each of the non-volatile memory die that determines it is a target, a first on-die termination configuration value; setting, by each of the non-volatile memory die that determines it is a non-target, a second on-die termination configuration value; configuring, by each of the target non-volatile memory die, its corresponding on-die termination circuit to provide a first impedance based, at least in part, on the first on-die termination configuration value; and concurrently with the configuring by each target non-volatile memory die, configuring, by each non-target non-volatile memory die, its corresponding on-die termination circuit to provide a second impedance based, at least

Abstract: A method of programming a memory device including a cell is provided. A first program pulse is applied to the cell. Middle program pulses are applied to the cell after the application of the first program pulse. A last program pulse is applied to the cell after the application of the middle program pulses. A pulse width of the last program pulse is wider than a pulse width of each of the middle program pulses and the first program pulse.

Abstract: The present disclosure provides a memory device that includes a memory array and a page buffer. The memory array includes a plurality of memory cells coupled to a bit line of the memory array. The page buffer is coupled to the plurality of memory cells via the bit line to sense stored data in the memory cells. The page buffer includes first, second, and third transistors coupled to the bit line, first and second nodes, a capacitance structure coupled to the first node, and a latch circuit coupled to the bit line via the first transistor. First terminals of the first, second, and third transistors are coupled to the first node. A second terminal of the second transistor is coupled to the second node. The third transistor amplifies a read margin voltage at the second node. The page buffer shortens a time of a read operation or verify operation.

Abstract: The disclosure provides a power supply circuit, a memory, a testing device, a memory system and an electronic device, relates to the memory technologies, and may reduce the testing time of the memory and the footprint occupation of the memory. The power supply circuit can include a voltage adjusting circuit and an oscillation circuit. A first voltage output terminal of the voltage adjusting circuit is coupled with a power supply input terminal of a delay chain circuit in the memory and coupled with a power supply input terminal of the oscillation circuit. The voltage adjusting circuit is configured to output a first voltage to the delay chain circuit and the oscillation circuit via the first voltage output terminal. The oscillation circuit is configured to generate a clock signal corresponding to the first voltage. The voltage adjusting circuit is also configured to receive an adjusting signal for adjust the first voltage.

Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods are disclosed. In some embodiments, the 3D memory device includes a peripheral circuitry formed on a first substrate. The peripheral circuitry includes a plurality of peripheral devices on a first side of the first substrate, a first interconnect layer, and a deep-trench-isolation on a second side of the first substrate, wherein the first and second sides are opposite sides of the first substrate and the deep-trench-isolation is configured to provide electrical isolation between at least two neighboring peripheral devices. The 3D memory device also includes a memory array formed on a second substrate. The memory array includes at least one memory cell and a second interconnect layer, wherein the second interconnect layer of the memory array is bonded with the first interconnect layer of the peripheral circuitry, and the peripheral devices are electrically connected with the memory cells.