Patents Assigned to Yangtze Memory Technologies Co., Ltd.
  • Patent number: 10896844
    Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack comprising a plurality of dielectric layer pairs disposed over a substrate; forming a first mask stack over the alternating layer stack; patterning the first mask stack to define a staircase region comprising a number of N sub-staircase regions over the alternating layer stack using a lithography process and N is greater than 1; forming a first staircase structure over the staircase region, the first staircase structure has a number of M steps at each of the staircase regions and M is greater than 1; and forming a second staircase structure on the first staircase structure, the second staircase structure has a number of 2*N*M steps at the staircase region.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: January 19, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Yu Ting Zhou
  • Publication number: 20210013088
    Abstract: A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a peripheral circuitry including first and second peripheral devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the first and second peripheral devices, and forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method includes bonding the first and second interconnect layers and forming an isolation trench through the first substrate and exposing a portion of the STI structure. The isolation trench is formed through a second side of the first substrate that is opposite to the first side. The method includes disposing an isolation material to form an isolation structure in the isolation trench and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.
    Type: Application
    Filed: December 30, 2019
    Publication date: January 14, 2021
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Liang Chen, Wei Liu, Cheng Gan
  • Publication number: 20210013303
    Abstract: Embodiments of a three-dimensional capacitor for a memory device and fabrication methods are disclosed. The method includes forming, on a first side of a first substrate, a peripheral circuitry having a plurality of peripheral devices, a first interconnect layer, a deep well and a first capacitor electrode. The method also includes forming, on a second substrate, a memory array having a plurality of memory cells and a second interconnect layer, and bonding the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array. The method further includes forming, on a second side of the first substrate, one or more trenches inside the deep well, disposing a capacitor dielectric layer on sidewalls of the one or more trenches, and forming capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches.
    Type: Application
    Filed: December 30, 2019
    Publication date: January 14, 2021
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Liang CHEN, Cheng GAN, Wei LIU, Shunfu CHEN
  • Patent number: 10892280
    Abstract: Embodiments of 3D memory devices having an inter-deck plug and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a first memory deck including interleaved conductor and dielectric layers above the substrate, a second memory deck including interleaved conductor and dielectric layers above the first memory deck, and a first and a second channel structure each extending vertically through the first or second memory deck. The first channel structure includes a first memory film and semiconductor channel along a sidewall of the first channel structure, and an inter-deck plug in an upper portion of the first channel structure and in contact with the first semiconductor channel. A lateral surface of the inter-deck plug is smooth. The second channel structure includes a second memory film and semiconductor channel along a sidewall of the second channel structure. The second semiconductor channel is in contact with the inter-deck plug.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: January 12, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Qianbin Xu, Haohao Yang, EnBo Wang, Yong Zhang, Jialan He
  • Patent number: 10892277
    Abstract: Embodiments of 3D memory devices having one or more high-? dielectric layers and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including a high-? dielectric layer above the substrate and a plurality of interleaved conductor and dielectric layers above the high-? dielectric layer, and a semiconductor plug disposed above the substrate and in an opening of the high-? dielectric layer.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: January 12, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Li Hong Xiao
  • Patent number: 10892276
    Abstract: Embodiments of three-dimensional (3D) memory devices having a memory layer that confines electron transportation and methods for forming the same are disclosed. A method for forming a 3D memory device includes the following operations. First, an initial channel hole can be formed in a structure. The structure can include a staircase structure. The structure can include a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset can be formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel can then be formed based on the channel hole. Further, a plurality of gate electrodes can be formed based on the plurality of second layers.
    Type: Grant
    Filed: December 22, 2018
    Date of Patent: January 12, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Jun Liu, Li Hong Xiao, Yu Ting Zhou
  • Patent number: 10892274
    Abstract: Embodiments of 3D memory devices and fabricating methods are disclosed. The method can comprise: forming an alternating dielectric stack on a substrate; forming a channel hole penetrating the alternating dielectric stack to expose a surface of the substrate; forming an epitaxial layer on a bottom of the channel hole; forming a functional layer covering a sidewall of the channel hole and a top surface of the epitaxial layer; forming a protecting layer covering the functional layer; removing portions of the functional layer and the protecting layer to form an opening to expose a surface of the epitaxial layer; expanding the opening laterally to increase an exposed area of the epitaxial layer at the bottom of the channel hole; and forming a channel structure on the sidewall of the channel hole and being in electrical contact with the epitaxial layer through the expanded opening.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: January 12, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yushi Hu, Qian Tao, Haohao Yang, Jin Wen Dong, Jun Chen, Zhenyu Lu
  • Patent number: 10892023
    Abstract: Embodiments of 3D memory devices and methods for operating the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes memory decks each including memory layers in a vertical direction. Each memory layer in a first memory deck is first programmed. The first programming includes applying a program voltage to the memory layer and a first channel pass voltage smaller than the program voltage to each rest of the memory layers. Each memory layer in a second memory deck above the first memory deck is second programmed. The second programming includes applying the program voltage to the memory layer and the first channel pass voltage to each rest of the memory layers. The second programming further includes applying a second channel pass voltage smaller than the first channel pass voltage to each memory layer in the first memory deck.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: January 12, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Ming Wang, Hong Tao Liu, Yali Song
  • Patent number: 10892275
    Abstract: Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: January 12, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jun Liu, Zongliang Huo
  • Publication number: 20210005625
    Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 7, 2021
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xiaowang DAI, Zhenyu LU, Jun CHEN, Qian TAO, Yushi HU, Jifeng ZHU, Jin Wen DONG, Ji XIA, Zhong ZHANG, Yan Ni LI
  • Publication number: 20210005621
    Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yushi HU, Zhenyu LU, Qian TAO, Jun CHEN, Simon Shi-Ning YANG, Steve Weiyi YANG
  • Patent number: 10886294
    Abstract: Embodiments of three-dimensional (3D) memory devices having a memory layer that confines electron transportation and methods for forming the same are disclosed. A method for forming a 3D memory device includes the following operations. An initial channel hole in a structure is formed. The structure includes a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers can be formed on a sidewall of the initial channel hole to form a channel hole. The channel hole with a channel-forming structure can be formed to form a semiconductor channel. The channel-forming structure can include a memory layer extending along a vertical direction. The plurality of second layers can then be replaced with a plurality of gate electrodes.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: January 5, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Jun Liu, Li Hong Xiao
  • Patent number: 10885990
    Abstract: A method of performing a programming operation to a three dimensional (3D) NAND memory device is disclosed. The method makes residual electrons trapped in storage regions of middle dummy memory cells of the unselected string of the 3D NAND memory device to be removed during the pre-charging phase, so as to reduce program disturb to the selected string which neighbors the unselected string.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: January 5, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xinlei Jia, Shan Li, Kaiwei Li, Jianquan Jia, Lei Jin, Kaikai You, Ying Cui, Yali Song, Wei Hou, Zhiyu Wang, Hongtao Liu
  • Patent number: 10886256
    Abstract: Embodiments of methods and systems for wafer bonding alignment compensation are disclosed. The method comprises bonding a first pair of wafers including a first wafer and a second wafer, wherein the first pair of wafers have a plurality of corresponding bonding alignment mark pairs each including a first bonding alignment mark on the first wafer and a second bonding alignment mark on the second wafer; measuring alignment positions of the plurality of bonding alignment mark pairs; determining a mean run-out misalignment between the first pair of wafers using the alignment measurement, wherein the mean run-out misalignment indicates a deformation of at least one of the first pair of wafers; and during bonding of a second pair of wafers, controlling a wafer deformation adjustment module to compensate for the run-out misalignment based on the mean run-out misalignment of the first pair of wafers.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: January 5, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Shuai Guo
  • Patent number: 10886291
    Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: January 5, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Wenguang Shi, Guanping Wu, Feng Pan, Xianjin Wan, Baoyou Chen
  • Publication number: 20200411538
    Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack on a substrate, forming a plurality of staircase regions where each staircase region has a staircase structure having a first number (M) of steps in a first direction; forming a first mask stack to expose a plurality of the staircase regions; removing (M) of the layer stacks in the exposed staircase regions; forming a second mask stack over the alternating layer stack to expose at least an edge of each of the staircase regions in a second direction; and repetitively, sequentially, removing a portion of (2M) of layer stacks and trimming the second mask stack.
    Type: Application
    Filed: August 27, 2020
    Publication date: December 31, 2020
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xiang Hui ZHAO, Zui Xin ZENG, Jun HU, Shi ZHANG, Baoyou CHEN
  • Publication number: 20200411541
    Abstract: A semiconductor device is provided. The semiconductor device includes a first substrate that has a first side for forming memory cells and a second side that is opposite to the first side. The semiconductor device also includes a doped region and a first connection structure. The doped region is formed in the first side of the first substrate and is electrically coupled to at least a source terminal of a transistor (e.g., a source terminal of an end transistor of multiple transistors that are connected in series). The first connection structure is formed over the second side of the first substrate and coupled to the doped region through a first VIA. The first VIA extends from the second side of the first substrate to the doped region.
    Type: Application
    Filed: December 12, 2019
    Publication date: December 31, 2020
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jin Yong Oh, Youn Cheul Kim
  • Publication number: 20200411543
    Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the memory device includes a stack structure having interleaved a plurality of conductor layers and a plurality of dielectric layers over a substrate along a vertical direction. The memory device also includes a channel structure extending in the stack structure along the vertical direction. A thickness of at least one of the plurality of conductor layers is nominally proportional to a width of the channel structure at the same depth.
    Type: Application
    Filed: April 30, 2020
    Publication date: December 31, 2020
    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Qiguang Wang, Wenxi Zhou
  • Publication number: 20200411535
    Abstract: Aspects of the disclosure provide a semiconductor device and a method to manufacture the semiconductor device. The semiconductor device includes a string of transistors stacked in a vertical direction over a substrate of the semiconductor device having a channel structure extending in the vertical direction. The string of transistors includes first, second, and third substrings of transistors that are arranged along first, second, and third portions of the channel structure, respectively. Gate structures of transistors in the first, second, and third substring are separated by respective first, second, and third insulating layers and the second insulating layers have a higher etch rate than that of the third insulating layers.
    Type: Application
    Filed: November 20, 2019
    Publication date: December 31, 2020
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Qiguang WANG, Gonglian Wu
  • Publication number: 20200411369
    Abstract: A method for fabricating a semiconductor device that includes forming a mask stack over a semiconductor structure. The mask stack has a first mask layer and a second mask layer, where the second mask layer is arranged between the first mask layer and the semiconductor structure. The method further includes patterning a first pattern in the mask stack. The first pattern includes a first opening having first sidewalls formed in the first mask layer, a second opening having second sidewalls formed in the second mask layer, and a third opening having third sidewalls formed in the semiconductor structure. The first, second, and third sidewalls of the respective openings of the first pattern are formed around a central axis, where the second sidewalls of the second opening are located further away from the central axis than both the first and third sidewalls of the first and third openings, respectively.
    Type: Application
    Filed: November 22, 2019
    Publication date: December 31, 2020
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventor: Gang Yang