Abstract: Examples of the present application provide a memory device and operating method thereof, a memory system, and a sensing circuit. Wherein the memory device includes: an array of memory cells; a first sensing circuit coupled to the array of memory cells through a first pair of data lines; a second sensing circuit coupled to the first pair of data lines through a second pair of data lines; an isolation circuit located between the first pair of data lines and the second pair of data lines; a control circuit configured to: in the first sensing phase, control the first sensing circuit to amplify the data signal to the first sensing signal, and control the isolation circuit to connect the first pair of data lines and the second pair of data lines.

Abstract: Examples of the present application disclose a memory device. The memory device includes: a memory cell array comprising memory cells that store a plurality of memory bits, the plurality of memory bits corresponding to a plurality of orders of read voltages, and a preset number of the memory cells forming a code word; and a peripheral circuit coupled with the memory cell array and configured to: acquire a first result of at least one code word corresponding to a target read voltage of a target order; acquire a predicted valley bottom voltage of the target order according to the first result of the at least one code word corresponding to the target read voltage of the target order and a level in which the target order is located; and determine a target valley bottom voltage of the target order based on the predicted valley bottom voltage of the target order.

Abstract: A memory, an operation method thereof, and a memory system are provided. The memory includes: a memory cell array including memory strings each including memory cells and top select transistors; top select gate lines coupled to top select transistors; word lines coupled to memory cells; and a peripheral circuit coupled to top select gate lines and word lines and configured to: apply a first pulse to a first word line of word lines, such that a voltage of the first word line reaches a first target voltage at a first time instant; apply a second pulse to a first top select gate line of top select gate lines adjacent to the first word line, such that a voltage of the first top select gate line reaches a second target voltage at a second time instant that is later than the first time instant.

Abstract: A semiconductor device includes a first substrate, a second substrate, a first connection structure, and a second connection structure. A transistor is formed in a first side of the first substrate. A doped region is formed in a first side of the second substrate. The first connection structure is formed over a second side of the second substrate, and coupled to the doped region through a first VIA that extends from the second side of the second substrate to the doped region. The second connection structure is formed over the first side of the first substrate, connected with the first connection structure via a through silicon VIA, and coupled to the transistor through a bonding VIA. The first substrate is bonded to the second substrate by the bonding VIA, with the first side of the first substrate and the first side of the second substrate being facing each other.

Abstract: A method for forming a 3D memory device includes forming an array wafer based on a first substrate having at least one cell region for forming a plurality of memory cells and at least one string structure region for forming a string structure; forming a first complementary metal-oxide-semiconductor (CMOS) wafer based on a second substrate having at least one string driver region corresponding to the at least one string structure region, and at least one page buffer high-voltage (HV) circuit region corresponding to the at least one cell region; forming a second CMOS wafer based on a third substrate having at least one page buffer region corresponding to the at least one cell region; and forming the 3D memory device based on the array wafer, the first CMOS wafer, and the second CMOS wafer stacked together.

Abstract: Example three-dimensional (3D) memory devices, methods, and memory systems for connecting vertical transistors and capacitors using connect structures are disclosed. One example method includes forming a first structure that includes multiple vertical transistors. A connect layer is formed over the first structure. The connect layer is etched to form connect structures, where each of the connect structures is coupled to a corresponding one of the vertical transistors. Multiple capacitors are formed over the connect layer, where each of the plurality of capacitors is coupled to a respective connect structure.

Abstract: The present disclosure provides a three-dimensional memory device and a manufacturing method thereof, and a three-dimensional memory. The three-dimensional memory device includes a first memory cell and at least one second memory cell sequentially stacked on the first memory cell. Each memory cell includes a first set of contacts, and a memory array device and a CMOS device that are stacked and electrically connected with each other, and the first set of contacts is disposed on a side of the memory array device facing away from the CMOS device and electrically connected with the CMOS device. The second memory cell further comprises a second set of contacts that is disposed on a side of the CMOS device facing away from the memory array device and electrically connected with the CMOS device.

Abstract: An example memory system includes a memory device and a memory controller. The memory device includes memory cells each configured to be in one of data states. The memory controller is configured to: perform a read operation using a test read voltage corresponding to a selected data state among the data states; acquire a count of memory cells each having a threshold voltage that satisfies a preset condition including: the threshold voltage being less than or equal to the test read voltage, or the threshold voltage being greater than or equal to the test read voltage; determine a difference between the count and an expected count; and acquire at least one read retry voltage according to the difference, a mapping relationship, and a read retry table, wherein the mapping relationship includes a correspondence between an expected voltage offset value and the difference.

Abstract: The present application discloses methods of operating a memory system, memory systems, hosts, and memory controllers. An example method includes receiving a read command, the read command including a first logical block address (LBA); based on a first attribute identifier corresponding to a first mapping table block in a compressed mapping table, determining a first physical address corresponding to the first LBA in the first mapping table block, the compressed mapping table including a plurality of attribute identifiers, the plurality of attribute identifiers corresponding to different mapping table blocks in a logical-to-physical (L2P) mapping table, an attribute identifier indicating whether physical addresses in a corresponding mapping table block are continuous, and the first mapping table block being the mapping table block in which the first LBA is located; and performing a read operation on a memory device based on the first physical address.

Abstract: A memory device includes a memory array including a first memory plane and a second memory plane, and a peripheral circuit coupled to the memory array and configured to perform an operation. The operation includes receiving a first instruction and input data, and in response to the first instruction, writing first data of the input data to the first memory plane and second data of the input data to the second memory plane. The second data is configured to indicate whether the first data has been performed with an inversion operation prior to transmission.

Abstract: According to one aspect of the present disclosure, a method for operating a memory is provided. The method may include receiving an erase resume command. The erase resume command may indicate a resume of an erase operation on a memory block in a memory. The method may include, if the erase operation is in an erase pulse phase, releasing, at a first time, a voltage of a special word line to which the memory block is connected in response to a quantity of erase suspends of the memory block being less than a threshold. The quantity of erase suspends may refer to a quantity that the erase operation is suspended in the erase pulse phase. The method may include releasing, at a second time, the voltage of the special word line in response to the quantity of erase suspends being greater than or equal to the threshold, wherein the second time is earlier than the first time.

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a stack structure includes interleaved dielectric layers and conductive layers, a channel structure extending in the stack structure, and a doped semiconductor layer arranged on the stack structure. The doped semiconductor layer covers an end of the channel structure and the stack structure, the channel structure includes a channel layer, and the channel layer includes a doped channel layer.

Abstract: The present disclosure provides a semiconductor package structure, a fabrication method, and a memory system. The semiconductor package structure includes a plurality of package bodies stacked in a first direction. At least one of the plurality of package bodies includes first interconnect structures extending in the first direction and a plurality of sub package bodies stacked in the first direction. Each of the plurality of sub package bodies includes a molding body and a device structure encapsulated in the molding body. The device structure includes a passive device. The passive device includes at least one of a resistor, a capacitor, and an inductor.

Abstract: The present application provides an operation method of a memory, a memory, and a memory system, and relates to the technical field of semiconductor chips. The memory includes a memory block and a plurality of word lines coupled to the memory block. The operation method includes: applying a pass voltage to the plurality of word lines after a first read operation and before a second read operation; applying the pass voltage to the plurality of word lines in a pre-turn-on stage of the second read operation; and applying a first read voltage to a first word line of the plurality of word lines in a read stage of the second read operation, wherein the pass voltage is greater than the first read voltage. In the present application, the pass voltage is applied to the plurality of word lines after the first read operation and before the second read operation.

Abstract: A memory device includes a memory array structure having a plurality of memory banks, each memory bank including a plurality of memory groups, each memory group having at least one memory block; and a peripheral structure stacked with the memory array structure in a vertical direction, and having a plurality of memory-group-driver circuits each corresponding to one of the plurality of memory groups, respectively, wherein each memory-group-driver circuit is coupled with word lines of at least one memory block of a corresponding one of memory groups, and overlaps with one of the at least one memory blocks in the vertical direction. Each memory-group-driver circuit may include a precharge-voltage-driver circuit configured to provide a precharge voltage to the word lines, and a discharge-voltage-driver circuit configured to provide a discharge voltage to the word lines.

Abstract: Disclosed in the present application are an operating method for a memory controller, a memory controller, a system, and an electronic device. The operating method can include, when detecting that remaining capacity of a used backup area in the memory is less than capacity required for redundancy check data to be written, determining a backup area to be used from the memory, determining valid redundancy check data belonging to garbage collection in the used backup area, and backing up the valid redundancy check data into the backup area to be used, and erasing the used backup area.

Abstract: A memory device includes a memory array and a control logic coupled to the memory array. The memory array includes memory blocks. Each memory block includes memory cell strings, and each memory cell string includes a first memory cell, second memory cells, and a third memory cell. The second memory cells are between the first memory cell and the third memory cell. The first memory cell is coupled to a bit line, the third memory cell is coupled to a source line, the first memory cell is coupled with a first dummy word line, the second memory cells are respectively coupled with second word lines, and the third memory cell is coupled with a third word line.

Abstract: An implementation of a memory device includes a stack structure having alternating first layers and dielectric layers. The stack structure has a first surface and a second surface opposite to the first surface. First contact structures include a conductive material. The first contact structures penetrate from the first surface into the stack structure to be in contact respectively with a first portion of first layers. Second contact structures include a conductive material. Each of the second contact structures penetrates from the second surface into the stack structure to be in contact respectively with a remainder portion of conductive layers other than the first portion of the first layers.

Abstract: Examples of the present disclosure disclose a memory device, a memory system, a memory controller and an operating method, the memory device includes: a preset number of the memory cells form one code word, and the multiple storage bits correspond to multiple pages respectively; at least one page corresponds to multiple stages, the multiple stages include a first stage and a second stage, and the read voltage corresponding to the second stage is less than the read voltage in the first stage; peripheral circuit coupled to the array of memory cells and configured to: obtain the target valley voltage in the first target stage; take the target valley voltage as a read voltage at which a read operation is performed on the at least one code word; and obtain the predicted valley voltage in the second target stage in accordance with the target valley voltage in the first target stage.

Abstract: A semiconductor device and methods for forming the same are provided. The semiconductor device includes an array of vertical transistors. Each transistor includes a semiconductor body extending in a vertical direction, and a gate structure located adjacent to a sidewall of the semiconductor body. The gate structures of each row of vertical transistors are connected with each other and extend along a first lateral direction to form a word line. A first word line of a first row of vertical transistors is located at a first side of the semiconductor bodies of the first row of vertical transistors along a second lateral direction perpendicular to the first lateral direction; and a second word line of a second row of vertical transistors adjacent to the first row of vertical transistors is located at a second side of the semiconductor bodies of the second row of vertical transistors along the second lateral direction.